Laser Processing For 3D Junctionless Transistor Fabrication

D. Bosch; P. Acosta Alba; S. Kerdiles; V. Benevent; C. Perrot; J. Lassarre; J. Richy; J. Lacord; B. Sklenard; L. Brunet; P. Batude; C. Fenouillet-Beranger; D. Lattard; J. P. Colinge; F. Balestra; F. Andrieu

Laser Processing For 3D Junctionless Transistor Fabrication

Applied Physics 2020-12-01 v1

Authors: D. Bosch , P. Acosta Alba , S. Kerdiles , V. Benevent , C. Perrot , J. Lassarre , J. Richy , J. Lacord , B. Sklenard , L. Brunet , P. Batude , C. Fenouillet-Beranger , D. Lattard , J. P. Colinge , F. Balestra , F. Andrieu

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Abstract

To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-silicon film featuring excellent roughness values (Rmax= 1.6nm and RMS=0.2nm). Guidelines for grain size optimization using nanosecond (ns) laser annealing are given.

Keywords

silicon physics materials science

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@article{arxiv.2011.15061,
  title  = {Laser Processing For 3D Junctionless Transistor Fabrication},
  author = {D. Bosch and P. Acosta Alba and S. Kerdiles and V. Benevent and C. Perrot and J. Lassarre and J. Richy and J. Lacord and B. Sklenard and L. Brunet and P. Batude and C. Fenouillet-Beranger and D. Lattard and J. P. Colinge and F. Balestra and F. Andrieu},
  journal= {arXiv preprint arXiv:2011.15061},
  year   = {2020}
}

Laser Processing For 3D Junctionless Transistor Fabrication

Abstract

Keywords

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