We present the design and simulation of a 30 μm thick 4H-SiC Low Gain Avalanche Diode (LGAD) optimized for high-voltage operation. A 2.4 μm thick epitaxially grown gain layer enables controlled internal amplification up to 1 kV reverse bias, while maintaining full depletion below 500 V. Electrical characteristics, including I-V, C-V, and gain behavior, were simulated in Synopsys Sentaurus Technology Computer-Aided Design (TCAD) using a quasi-1D geometry and verified across process-related variations in gain layer parameters. To ensure high-voltage stability and proper edge termination, a guard structure combining deep etched trenches and deep p+ junction termination extension (JTE) implants was designed. TCAD simulations varying the guard structure dimensions yielded an optimized design with a breakdown voltage above 2.4 kV. A corresponding wafer run is currently processed at IMB-CNM, Barcelona.
@article{arxiv.2510.14531,
title = {Design and simulation of a 4H-SiC low gain avalanche diode with trench-isolation},
author = {Sebastian Onder and Philipp Gaggl and Jürgen Burin and Andreas Gsponer and Matthias Knopf and Simon Waid and Neil Moffat and Giulio Pellegrini and Thomas Bergauer},
journal= {arXiv preprint arXiv:2510.14531},
year = {2025}
}