Accelerated Lifetime Testing and Analysis of Delta-doped Silicon Test Structures
Abstract
As transistor features shrink beyond the 2 nm node, studying and designing for atomic scale effects become essential. Being able to combine conventional CMOS with new atomic scale fabrication routes capable of creating 2D patterns of highly doped phosphorus layers with atomic precision has implications for the future of digital electronics. This work establishes the accelerated lifetime tests of such doped layers, showing that these materials survive high current (>3.0 MA/cm2) and 300C for greater than 70 days and are still electrically conductive. The doped layers compare well to failures in traditional metal layers like aluminum and copper where mean time to failure at these temperatures and current densities would occur within hours. It also establishes that these materials are more stable than metal features, paving the way toward their integration with operational CMOS.
Cite
@article{arxiv.2110.11580,
title = {Accelerated Lifetime Testing and Analysis of Delta-doped Silicon Test Structures},
author = {Connor Halsey and Jessica Depoy and DeAnna M. Campbell and Daniel R. Ward and Evan M. Anderson and Scott W. Schmucker and Jeffrey A. Ivie and Xujiao Gao and David A. Scrymgeour and Shashank Misra},
journal= {arXiv preprint arXiv:2110.11580},
year = {2022}
}
Comments
In IEEE Trans. Dev. Mater. Rel. (2022). Copyright 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, including reprinting/republishing this material for advertising or promotional purposes, collecting new collected works for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works