In this paper, we have worked out a pseudo two dimensional (2D) analytical model for surface potential and drain current of a long channel p-type Dual Material Gate (DMG) Gate All-Around (GAA) nanowire Tunneling Field Effect Transistor (TFET). The model incorporates the effect of drain voltage, gate metal work functions, thickness of oxide and silicon nanowire radius. The model does not assume a fully depleted channel. With the help of this model we have demonstrated the accumulation of charge at the interface of the two gates. The accuracy of the model is tested using the 3D device simulator Silvaco Atlas.
@article{arxiv.1406.5402,
title = {A Pseudo 2D-analytical Model of Dual Material Gate All-Around Nanowire Tunneling FET},
author = {Rajat Vishnoi and M. Jagadesh Kumar},
journal= {arXiv preprint arXiv:1406.5402},
year = {2014}
}
Comments
arXiv admin note: text overlap with arXiv:1405.6364