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Analog circuit design can be formulated as a non-linear constrained optimisation problem that can be solved using any suitable optimisation algorithms. Different optimisation techniques have been reported to reduce the design time of analog…

This short paper presents a work on the design of low noise microwave amplifiers using particle swarm optimization (PSO) technique. Particle Swarm Optimization is used as a method that is applied to a single stage amplifier circuit to meet…

Growing interest in semiconductor workforce development has generated demand for platforms capable of supporting large numbers of independent hardware designs for research and training without imposing high per-project overhead. Traditional…

This paper investigates the optimization of reconfigurable intelligent surface (RIS) in an integrated sensing and communication (ISAC) system. \red{To meet the demand of growing number of devices, power domain non-orthogonal multiple access…

This paper presents a scalable beamforming design for maximizing the spectral efficiency (SE) of multi-reconfigurable intelligent surface (RIS)-aided communications through joint optimization of the precoder and RIS phase shifts in…

We investigate the performance of a multiple reconfigurable intelligence surface (RIS)-aided millimeter wave (mmWave) beamspace multiple-input multiple-output (MIMO) system with multiple users (UEs). We focus on a challenging scenario in…

Low power oriented circuit optimization consists in selecting the best alternative between gate sizing, buffer insertion and logic structure transformation, for satisfying a delay constraint at minimum area cost. In this paper we used a…

As the Internet of Things (IOT) is growing rapidly, there is an emerging need to facilitate development of IOT devices in the design cycle while optimized performance is obtained in the field of operation. This paper develops…

This paper proposes an ultra-low power crypto-engine achieving sub-pJ/bit energy and sub-1K$\mu$$m^2$ in 40nm CMOS, based on the Simon cryptographic algorithm. Energy and area efficiency are pursued via microarchitectural exploration,…

This paper considers a reconfigurable intelligent surface (RIS)-aided millimeter wave (mmWave) downlink communication system where hybrid analog-digital beamforming is employed at the base station (BS). We formulate a power minimization…

This paper presents a compact low-power, low-noise bioamplifier for multi-channel electrode arrays, aimed at recording action potentials. The design we put forth attains a notable decrease in both size and power consumption. This is…

This paper presents a new real-time intelligent optimization algorithm to minimize the voltage harmonics of a multilevel inverter. Hybrid Genetic algorithm /Particle swarm optimization algorithm is employed in a real-time simulation to…

Managing insertion losses, polarizations and device footprint is crucial in developing large-scale photonic integrated circuits (PICs). This paper presents a solution to these critical challenges by designing a semiconductor optical…

Massive multiple-input multiple-output (MIMO) technology facilitates huge increases in the capacity of wireless channels, while non-orthogonal multiple access (NOMA) addresses the problem of limited resources in traditional orthogonal…

Cell-Free Massive Multiple-input Multiple-output (mMIMO) consists of many access points (APs) in a coverage area that jointly serve the users. These systems can significantly reduce the interference among the users compared to conventional…

This study focuses on the optimization of a single-cell multi-user multiple-input multiple-output (MIMO) system with multiple large-size reconfigurable intelligent surfaces (RISs). The overall transmit power is minimized by optimizing the…

Pinching antenna system (PASS) configures the positions of pinching antennas (PAs) along dielectric waveguides to change both large-scale fading and small-scale scattering, which is known as pinching beamforming. A novel non-orthogonal…

Today every circuit has to face the power consumption issue for both portable device aiming at large battery life and high end circuits avoiding cooling packages and reliability issues that are too complex. It is generally accepted that…

This paper studies an architecture with digitally controllable gain and power consumption to mitigate the impact of process variations on CMOS low-noise amplifiers (LNAs). A \SI{130}{nm}, \SI{1.2}{V} LNA implementing the proposed…

Fast combinational multipliers with large bit widths can occupy significant silicon area, which also drives up power consumption. Area can be reduced through resource sharing (i.e., folding) at the expense of lower throughput, which is…