Using Floating Gate Memory to Train Ideal Accuracy Neural Networks

Sapan Agarwal; Diana Garland; John Niroula; Robin B; Jacobs-Gedrim; Alex Hsia; Michael S. Van Heukelom; Elliot Fuller; Bruce Draper; Matthew J. Marinella

Using Floating Gate Memory to Train Ideal Accuracy Neural Networks

Emerging Technologies 2019-02-28 v2 Disordered Systems and Neural Networks

Authors: Sapan Agarwal , Diana Garland , John Niroula , Robin B , Jacobs-Gedrim , Alex Hsia , Michael S. Van Heukelom , Elliot Fuller , Bruce Draper , Matthew J. Marinella

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Abstract

Floating gate SONOS (Silicon-Oxygen-Nitrogen-Oxygen-Silicon) transistors can be used to train neural networks to ideal accuracies that match those of floating point digital weights on the MNIST dataset when using multiple devices to represent a weight or within 1% of ideal accuracy when using a single device. This is enabled by operating devices in the subthreshold regime, where they exhibit symmetric write nonlinearities. A neural training accelerator core based on SONOS with a single device per weight would increase energy efficiency by 120X, operate 2.1X faster and require 5X lower area than an optimized SRAM based ASIC.

Keywords

memristor mixed precision training fpga accelerator

Cite

@article{arxiv.1901.10570,
  title  = {Using Floating Gate Memory to Train Ideal Accuracy Neural Networks},
  author = {Sapan Agarwal and Diana Garland and John Niroula and Robin B and Jacobs-Gedrim and Alex Hsia and Michael S. Van Heukelom and Elliot Fuller and Bruce Draper and Matthew J. Marinella},
  journal= {arXiv preprint arXiv:1901.10570},
  year   = {2019}
}

Using Floating Gate Memory to Train Ideal Accuracy Neural Networks

Abstract

Keywords

Cite

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