Non-volatile memory arrays can deploy pre-trained neural network models for edge inference. However, these systems are affected by device-level noise and retention issues. Here, we examine damage caused by these effects, introduce a mitigation strategy, and demonstrate its use in fabricated array of SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) devices. On MNIST, fashion-MNIST, and CIFAR-10 tasks, our approach increases resilience to synaptic noise and drift. We also show strong performance can be realized with ADCs of 5-8 bits precision.
@article{arxiv.2004.00802,
title = {Device-aware inference operations in SONOS nonvolatile memory arrays},
author = {Christopher H. Bennett and T. Patrick Xiao and Ryan Dellana and Vineet Agrawal and Ben Feinberg and Venkatraman Prabhakar and Krishnaswamy Ramkumar and Long Hinh and Swatilekha Saha and Vijay Raghavan and Ramesh Chettuvetty and Sapan Agarwal and Matthew J. Marinella},
journal= {arXiv preprint arXiv:2004.00802},
year = {2020}
}
Comments
To be presented at IEEE International Physics Reliability Symposium (IRPS) 2020