English

A New MRAM-based Process In-Memory Accelerator for Efficient Neural Network Training with Floating Point Precision

Distributed, Parallel, and Cluster Computing 2020-05-13 v2 Hardware Architecture Emerging Technologies Machine Learning

Abstract

The excellent performance of modern deep neural networks (DNNs) comes at an often prohibitive training cost, limiting the rapid development of DNN innovations and raising various environmental concerns. To reduce the dominant data movement cost of training, process in-memory (PIM) has emerged as a promising solution as it alleviates the need to access DNN weights. However, state-of-the-art PIM DNN training accelerators employ either analog/mixed signal computing which has limited precision or digital computing based on a memory technology that supports limited logic functions and thus requires complicated procedure to realize floating point computation. In this paper, we propose a spin orbit torque magnetic random access memory (SOT-MRAM) based digital PIM accelerator that supports floating point precision. Specifically, this new accelerator features an innovative (1) SOT-MRAM cell, (2) full addition design, and (3) floating point computation. Experiment results show that the proposed SOT-MRAM PIM based DNN training accelerator can achieve 3.3×\times, 1.8×\times, and 2.5×\times improvement in terms of energy, latency, and area, respectively, compared with a state-of-the-art PIM based DNN training accelerator.

Keywords

Cite

@article{arxiv.2003.01551,
  title  = {A New MRAM-based Process In-Memory Accelerator for Efficient Neural Network Training with Floating Point Precision},
  author = {Hongjie Wang and Yang Zhao and Chaojian Li and Yue Wang and Yingyan Lin},
  journal= {arXiv preprint arXiv:2003.01551},
  year   = {2020}
}

Comments

Accepted by the IEEE International Symposium on Circuits and Systems 2020 (ISCAS'2020)

R2 v1 2026-06-23T14:02:07.184Z