Tree Parity Machine Rekeying Architectures
密码学与安全
2007-05-23 v1 硬件体系结构
摘要
The necessity to secure the communication between hardware components in embedded systems becomes increasingly important with regard to the secrecy of data and particularly its commercial use. We suggest a low-cost (i.e. small logic-area) solution for flexible security levels and short key lifetimes. The basis is an approach for symmetric key exchange using the synchronisation of Tree Parity Machines. Fast successive key generation enables a key exchange within a few milliseconds, given realistic communication channels with a limited bandwidth. For demonstration we evaluate characteristics of a standard-cell ASIC design realisation as IP-core in 0.18-micrometer CMOS-technology.
引用
@article{arxiv.cs/0502062,
title = {Tree Parity Machine Rekeying Architectures},
author = {Markus Volkmer and Sebastian Wallner},
journal= {arXiv preprint arXiv:cs/0502062},
year = {2007}
}