A near memory hardware accelerator, based on a novel direct path computational model, for real-time emulation of radio frequency systems is demonstrated. Our evaluation of hardware performance uses both application-specific integrated circuits (ASIC) and field programmable gate arrays (FPGA) methodologies: 1). The ASIC testchip implementation, using TSMC 28nm CMOS, leverages distributed autonomous control to extract concurrency in compute as well as low latency. It achieves a 518 MHz per channel bandwidth in a prototype 4-node system. The maximum emulation range supported in this paradigm is 9.5 km with 0.24μs of per-sample emulation latency. 2). The FPGA-based implementation, evaluated on a Xilinx ZCU104 board, demonstrates a 9-node test case (two Transmitters, one Receiver, and 6 passive reflectors) with an emulation range of 1.13 km to 27.3 km at 215 MHz bandwidth.
@article{arxiv.2406.08714,
title = {Real-time Digital RF Emulation -- II: A Near Memory Custom Accelerator},
author = {Mandovi Mukherjee and Xiangyu Mao and Nael Rahman and Coleman DeLude and Joe Driscoll and Sudarshan Sharma and Payman Behnam and Uday Kamal and Jongseok Woo and Daehyun Kim and Sharjeel Khan and Jianming Tong and Jamin Seo and Prachi Sinha and Madhavan Swaminathan and Tushar Krishna and Santosh Pande and Justin Romberg and Saibal Mukhopadhyay},
journal= {arXiv preprint arXiv:2406.08714},
year = {2024}
}