We report the design-technology co-optimization (DTCO) scheme to develop a 28-nm cryogenic CMOS (Cryo-CMOS) technology for high-performance computing (HPC). The precise adjustment of halo implants manages to compensate the threshold voltage (VTH) shift at low temperatures. The optimized NMOS and PMOS transistors, featured by VTH<0.2V, sub-threshold swing (SS)<30 mV/dec, and on-state current (Ion)>1.2mA/um at 77K, warrant a reliable sub-0.6V operation. Moreover, the enhanced driving strength of Cryo-CMOS inherited from a higher transconductance leads to marked improvements in elevating the ring oscillator frequency by 20%, while reducing the power consumption of the compute-intensive cryogenic IC system by 37% at 77K.
@article{arxiv.2411.03099,
title = {Optimized Cryo-CMOS Technology with VTH<0.2V and Ion>1.2mA/um for High-Peformance Computing},
author = {Chang He and Yue Xin and Longfei Yang and Zewei Wang and Zhidong Tang and Xin Luo and Renhe Chen and Zirui Wang and Shuai Kong and Jianli Wang and Jianshi Tang and Xiaoxu Kang and Shoumian Chen and Yuhang Zhao and Shaojian Hu and Xufeng Kou},
journal= {arXiv preprint arXiv:2411.03099},
year = {2024}
}