On CC\textsuperscript{0} Lower Bounds for AND via Torus Polynomials
摘要
We explore a torus polynomial approximation based approach towards a long-standing question: whether can be computed by circuits - the class of constant-depth polynomial size circuits containing gates for some . Bhrushundi et al. (ITCS 2019) introduced torus polynomial approximations as an approach for proving lower bounds against - a class containing with circuits comprising , and gates. We show how lower bounds for torus polynomials approximating can be used to make progress on this question. Using lower bounds on the degree of symmetric torus polynomials approximating from Krishan and Vishwanathan (ITCS 2026), we prove size lower bounds for symmetric -circuits computing . More precisely, we prove that any depth symmetric circuit requires size to compute . A key ingredient in our proof is an argument that we can construct symmetric torus polynomials to approximate symmetric circuits. Our construction exhibits an explicit correspondence between the symmetry of the circuit and that of the polynomial. Using this, we also establish lower bounds for weaker notions of circuit symmetry. Lower bounds for symmetric circuits were also independently established by Pago (ICALP 2026) using different techniques. In the asymmetric regime, we establish degree upper bounds for depth three circuits of the form where is a semiprime. This circuit class is a special case of the constant degree hypothesis, introduced by Barrington, Straubing and Therien (Inf. and Comp., 1990), where could be an arbitrary composite number. We argue that improved lower bounds for asymmetric torus polynomials approximating imply size lower bounds for semiprime and hence progress on the constant-degree hypothesis.
引用
@article{arxiv.2607.10236,
title = {On CC\textsuperscript{0} Lower Bounds for AND via Torus Polynomials},
author = {Vaibhav Krishan and Jayalal Sarma},
journal= {arXiv preprint arXiv:2607.10236},
year = {2026}
}