GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator

Jan Gray

GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator

Hardware Architecture 2016-06-06 v1

Authors: Jan Gray

Abstract

GRVI is an FPGA-efficient RISC-V RV32I soft processor. Phalanx is a parallel processor and accelerator array framework. Groups of processors and accelerators form shared memory clusters. Clusters are interconnected with each other and with extreme bandwidth I/O and memory devices by a 300- bit-wide Hoplite NOC. An example Kintex UltraScale KU040 system has 400 RISC-V cores, peak throughput of 100,000 MIPS, peak shared memory bandwidth of 600 GB/s, NOC bisection bandwidth of 700 Gbps, and uses 13 W.

Keywords

computer architecture fpga accelerator

Cite

@article{arxiv.1606.01037,
  title  = {GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator},
  author = {Jan Gray},
  journal= {arXiv preprint arXiv:1606.01037},
  year   = {2016}
}

Comments

Presented at 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016) arXiv:1605.08149

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