Gate-level simulation of logical state preparation
量子物理
2007-05-23 v1
摘要
Quantum error correction and fault-tolerant quantum computation are two fundamental concepts which make quantum computing feasible. While providing a theoretical means with which to ensure the arbitrary accuracy of any quantum circuit, fault-tolerant error correction is predicated upon the robust preparation of logical states. An optimal direct circuit and a more complex fault-tolerant circuit for the preparation of the [[7,1,3]] Steane logical-zero are simulated in the presence of discrete quantum errors to quantify the regime within which fault-tolerant preparation of logical states is preferred.
引用
@article{arxiv.quant-ph/0608112,
title = {Gate-level simulation of logical state preparation},
author = {A. M. Stephens and S. J. Devitt and A. G. Fowler and J. C. Ang and L. C. L. Hollenberg},
journal= {arXiv preprint arXiv:quant-ph/0608112},
year = {2007}
}
备注
8 pages, 2 figures