ACTreS: Analog Clock Tree Synthesis
Abstract
This paper describes a graph-theoretic formalism and a flow that, to a great extent, automate the design of clock trees in Sampled-Data Analog Circuits (SDACs). The current practice for clock tree design of SDACs is a manual process, which is time-consuming and error-prone. Clock tree design in digital domain, however, is fully automated and is carried out by Clock Tree Synthesis (CTS) software. In spite of critical differences, SDAC clock tree design problem has fundamental similarities with its digital counterpart. We exploited these similarities and built a design flow and tool set, which uses commercial digital CTS software as an intermediate step. We will explain our flow using a 0.18 micron 10-bit 60 MHz 2-stage pipelined differential-input flash analog-to-digital converter as a test circuit.
Cite
@article{arxiv.2108.12897,
title = {ACTreS: Analog Clock Tree Synthesis},
author = {Bilgiday Yuce and H. Fatih Ugurdag and Iskender Agi and Gokhan Guner and Vahap Baris Esen and Seyrani Korkmaz and I. Faik Baskaya and Günhan Dündar},
journal= {arXiv preprint arXiv:2108.12897},
year = {2021}
}
Comments
12 pages, 24 figures, 2 tables