A Novel Design for SRAM Bitcell with 3-Complementary-FETs

The complementary field-effect transistors (CFETs), featuring vertically stacked n/p-FETs, enhance integration density and significantly reduce the area of standard cells such as static random-access memory (SRAM). However, the advantage of area scaling through CFETs is hindered by the imbalance in N/P transistor counts (typically 4N/2P) within SRAM cells. In this work, we propose a novel 6T-SRAM design using three sets of CFETs, achieved by vertically stacking two n-FET pass-gate (PG) transistors via the CFET architecture. Through TCAD simulations, we optimize channel doping concentration and the number of top/bottom nanosheets (NS), demonstrating that junctionless accumulation mode (JAM) devices outperform inversion mode (IM) devices for PG and pull-down (PD) transistors. The proposed design achieves a 37% area reduction in SRAM standard cell layout compared to conventional CFET-based SRAM. With optimized parameters (n-type doping of $1\times10^{15}$ cm$^{-3}$ and '1B4T' NS configuration), the 3-CFET SRAM exhibits superior write margin (349.60 mV) and write delay (54.4 ps). This work advances SRAM design within the CFET framework, offering a scalable solution for next-generation memory technologies.