Related papers: The Large Analog Bandwidth Recorder And Digitizer …

This paper investigates a hardware-efficient massive multiple-input multiple-output integrated sensing and communication (MIMO-ISAC) system with 1-bit analog-to-digital converters (ADCs)/digital-to-analog converters (DACs). The proposed…

In this work, a 3.5 GS/s voltage-controlled oscillator (VCO) analog-to-digital converter (ADC) using multi-stage noise shaping (MASH) is presented. This 28nm CMOS ADC achieves second-order noise shaping in an easily-scalable, open-loop…

With present-day detectors in high energy physics one often faces fast analog pulses of a few nanoseconds length which cover large dynamic ranges. In many experiments both amplitude and timing information have to be measured with high…

We present the first single-input multiple-output (SIMO) receiver ASIC that jointly performs jammer mitigation, channel estimation, and data detection. The ASIC implements a recent algorithm called siMultaneous mitigAtion, Estimation, and…

Analog to digital converters (ADCs) act as a bridge between the analog and digital domains. Two important attributes of any ADC are sampling rate and its dynamic range. For bandlimited signals, the sampling should be above the Nyquist rate.…

The design and performance of a fully-synchronous multi-GHz analog transient waveform recorder I.C. ("SST") with fast and flexible trigger capabilities is presented. The SST's objective is to provide multi-GHz sample rates with…

We report on the design and performance of a mixed-signal application specific integrated circuit (ASIC) dedicated to avalanche photodiodes (APDs) in order to detect hard X-ray emissions in a wide energy band onboard the International Space…

In a high-speed coherent optical transmission system, typically the signals obtained at the receiver front-end are digitized using very high-speed ADCs and then processed in the digital domain to remove optical channel impairments. In this…

The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on…

This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver…

In this letter, we investigate the robust beamforming design for an integrated sensing and communication (ISAC) system featuring low-resolution digital-to-analog converters (DACs) and analog-to-digital converters (ADCs). Taking into account…

Resistive Silicon Detectors (RSD, also known as AC-LGAD) are innovative silicon sensors, based on the LGAD technology, characterized by a continuous gain layer that spreads across the whole sensor active area. RSDs are very promising…

The power consumption of high-speed, high-resolution analog to digital converters (ADCs) is a limiting factor in implementing large-bandwidth mm-wave communication systems. A mitigating solution, which has drawn considerable recent…

We present a control and measurement setup for superconducting qubits based on Xilinx 16-channel radio-frequency system-on-chip (RFSoC) device. The proposed setup consists of four parts: multiple RFSoC boards, a setup to synchronise every…

The Low-Level RF (LLRF) control circuits of linear accelerators (LINACs) are conventionally realized with heterodyne based architectures, which have analog RF mixers for up and down conversion with discrete data converters. We have…

In this paper, an on-chip photonic sampled and quantized analog-to-digital converter (ADC) on thin-film lithium niobate platform is experimentally demonstrated. Using two phase modulators as a sampler and a 5$\times$5 multimode interference…

We present the architecture, design and first test results of SPIDER, the first prototype of a TSMC CMOS 65 nm ASIC designed for the time measurement path of LHCb Electromagnetic Calorimeter after LS4 Upgrade. The main requirements for the…

This paper presents the design and characterisation of a front-end prototype ASIC for the ATLAS High Granularity Timing Detector, which is planned for the High-Luminosity phase of the LHC. This prototype, called ALTIROC1, consists of a…

PARISROC is a complete read out chip, in AMS SiGe 0.35 micron technology [1], for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by the French…

We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS…