Related papers: Trap-Enhanced Steep-Slope Negative-Capacitance FET…
A consistent and widely accepted physical basis for interpretation of charge transport in amorphous oxide semiconductor (AOS) field-effect transistors (FETs), and more generally device physics, has been hampered by uncertainties in…
In this paper we propose a modified structure of TFET incorporating ferroelectric oxide as the complementary gate dielectric operating in negative capacitance zone, called the Negative Capacitance Tunnel FET (NCTFET). The proposed device…
Steep-slope $\beta$-Ga$_2$O$_3$ nano-membrane negative capacitance field-effect transistors (NC-FETs) are demonstrated with ferroelectric hafnium zirconium oxide in gate dielectric stack. Subthreshold slope less than 60 mV/dec at room…
The device concept of ferroelectric-based negative capacitance (NC) transistors offers a promising route for achieving energy-efficient logic applications that can outperform the conventional semiconductor technology, while viable operation…
We show that it is possible to reach one of the ultimate goals of organic electronics: producing organic field-effect transistors with trap densities as low as in the bulk of single crystals. We studied the spectral density of localized…
Ion-Sensitive Field-Effect Transistors (ISFETs) form a wide-spread technology for sensing, thanks to their label-free detection and intrinsic CMOS compatibility. Their current sensitivity, {\Delta}ID/ID, for a given {\Delta}pH, however, is…
As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor…
Field-effect transistors (FETs) with single gates are adversely affected by short channel effects such as drain-induced barrier lowering (DIBL) and increases in the magnitude of sub-threshold swing as the channel length is reduced.…
We report on measurements and modeling of FE HfZrO/SiO2 Ferroelectric-Dielectric (FE-DE) FETs which indicate that many of the phenomena attributed to Negative Capacitance can be explained by a delayed response of ferroelectric domain…
$\beta$-Ga$_{2}$O$_{3}$ based enhancement mode transistor designs are critical for the realization of low loss, high efficiency next generation power devices with rudimentary driving circuits. A novel approach towards attaining a high…
Traditional transistors based on complementary metal-oxide-semiconductor (CMOS) and metal-oxide-semiconductor field-effect transistors (MOSFETs) are facing significant limitations as device scaling reaches the limits of Moore's Law. These…
Physics based numerical simulation has been carried out to probe the sub-gap density of states (DOS) and underlying electron transport properties of amorphous oxide based thin film transistors (TFTs). The DOS model of TFTs consists of…
It is well known that conventional Field Effect Transistors (FET's) require a change in the channel potential of at least 60 mV at 300K to effect a change in the current by a factor of ten, and this minimum subthreshold slope S puts a lower…
The performance of n-type amorphous oxide semiconductor thin-film transistors (TFTs) is largely controlled by the density of states (DoS) near the conduction band mobility edge. Here, the full subgap DoS of amorphous InGaZnO (a-IGZO) TFTs,…
Gate bias stress instability in organic field-effect transistors (OFETs) is a major conceptual and device issue. This effect manifests itself by an undesirable shift of the transfer characteristics and is associated with long term charge…
Back-end-of-line (BEOL) logic integration is emerging as a complementary scaling path to supplement front-end-of-line (FEOL) Silicon. Among various options for BEOL logic, Carbon Nanotube Field-Effect Transistors (CNFETs) have been…
In this paper, we take a fresh look at the physics and operation of Negative Capacitance FETs, and provide unambiguous feedback to the device designers by examining NC-FETs' design space for sub-60 mV/dec Subthreshold Swing (SS).…
This work presents a novel monolithic 3D (M3D) FPGA architecture that leverages stackable back-end-of-line (BEOL) transistors to implement configuration memory and pass gates, significantly improving area, latency, and power efficiency. By…
In this letter, the transient behavior of a ferroelectric (FE) metal-oxide-semiconductor (MOS) capacitor is theoretically investigated with a series resistor. It is shown that compared to a conventional high-k dielectric MOS capacitor, a…
In this paper, through careful calibration, we demonstrate the possibility of using a single set of models and parameters to model the ON current and Sub-threshold Slope (SS) of an nMOSFET at 300K and 5K using Technology Computer-Aided…