Related papers: A 10-bit SAR ADC with 1.5x Input Range

This paper describes a new all-digital technique for calibration of the mismatches in time-interleaved analog-to-digital converters (TIADCs) to reduce the circuit area. The proposed technique gives the first order approximation of the gain…

Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform…

In error-tolerant applications, approximate adders have been exploited extensively to achieve energy efficient system designs. Mean error distance is one of the important error metrics used as a performance measure of approximate adders. In…

In this paper, we investigate the capacity of massive multiple-input multiple-output (MIMO) systems corrupted by complex-valued additive white Gaussian noise (AWGN) when both the transmitter and the receiver employ 1-bit digital-to-analog…

We developed a new front-end application specific integrated circuit (ASIC) for the upgrade of the Maia x-ray microprobe. The ASIC instruments 32 configurable front-end channels that perform either positive or negative charge amplification,…

Analog-to-digital conversion (ADC) is a key bottleneck in scaling DSP-centric receiver architectures to multiGigabit/s speeds. Recent information-theoretic results, obtained under ideal channel conditions (perfect synchronization, no…

Use of low resolution analog to digital converters (ADCs) is an effective way to reduce the high power consumption of millimeter wave (mmWave) receivers. In this paper, a receiver with low resolution ADCs based on adaptive thresholds is…

Digital beamforming and waveform generation techniques in MIMO radar offer enormous advantages in terms of flexibility and performance compared to conventional radar systems based on analog implementations. To allow for such fully digital…

Transformer inference requires high compute accuracy; achieving this using analog CIMs has been difficult due to inherent computational errors. To overcome this challenge, we propose a Capacitor-Reconfiguring CIM (CR-CIM) to realize high…

The quantum charge-coupled device (QCCD) is one of the notable architectures to achieve large-scale trapped-ion quantum computers. To realize QCCD architecture, ions must be transported quickly while minimizing motional excitation.…

In this letter, we investigate the uplink of a reconfigurable intelligent surface (RIS)-aided millimeter-wave (mmWave) multi-user system. In the considered system, however, problems with hardware cost and power consumption arise when…

We present the design of a low-power 4-bit 1GS/s folding-flash ADC with a folding factor of two. The design of a new unbalanced double-tail dynamic comparator affords an ultra-low power operation and a high dynamic range. Unlike the…

We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS…

As an important part of the field programmable gate array (FPGA) market, Intel FPGA has also great potential for implementation of time-to-digital convertor (TDC). In this paper, the basic tapped delay line (TDL) TDC structure is adapted in…

Deep learning-based super-resolution (SR) is challenging to implement in resource-constrained edge devices for resolutions beyond full HD due to its high computational complexity and memory bandwidth requirements. This paper introduces an…

The use of one-bit analog-to-digital converters (ADCs) is a practical solution for reducing cost and power consumption in massive Multiple-Input-Multiple-Output (MIMO) systems. However, the distortion caused by one-bit ADCs makes the data…

Analog-Based In-Memory Computing (AIMC) inference accelerators can be used to efficiently execute Deep Neural Network (DNN) inference workloads. However, to mitigate accuracy losses, due to circuit and device non-idealities, Hardware-Aware…

This paper presents a switch-type attenuator working from 20 to 100 GHz. The attenuator adopts a capacitive compensation technique to reduce phase error. The small resistors in this work are implemented with metal lines to reduce the…

Deep neural networks are widely deployed in many fields. Due to the in-situ computation (known as processing in memory) capacity of the Resistive Random Access Memory (ReRAM) crossbar, ReRAM-based accelerator shows potential in accelerating…

For 5G it will be important to leverage the available millimeter wave spectrum. To achieve an approximately omni- directional coverage with a similar effective antenna aperture compared to state of the art cellular systems, an antenna array…