Related papers: A 16.28 ppm/$^\circ$C Temperature Coefficient, 0.5…

High linear voltage references circuitry are designed and implemented in TSMC 0.18$\mu$m CMOS technology. Previous research has proposed the use of MOS transistors operating in the weak inversion region to replace the bipolar devices in…

Sensor nodes and IoT systems require blocks that not only consume low power but also have good accuracy. Voltage reference generators are also considered important building blocks in sensor interface circuits. This paper presents a solution…

The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions. However, while recent voltage references can meet most of…

In many applications, the ability of current references to cope with process, voltage, and temperature (PVT) variations is critical to maintaining system-level performance. However, temperature-independent current references operating in…

This paper presents a fully-integrated CMOS temperature sensor for densely-distributed thermal monitoring in systems on chip supporting dynamic voltage and frequency scaling. The sensor front-end exploits a sub-threshold PMOS-based circuit…

Internet-of-Things (IoT) applications require nW-power current references that are robust to process, voltage and temperature (PVT) variations, to maintain the performance of IoT sensor nodes in a wide range of operating conditions.…

This paper demonstrates the use of voltage noise thermometry, with a cross-correlation technique, as a dissipation-free method of thermometry inside a CMOS integrated circuit (IC). We show that this technique exhibits broad agreement with…

In recent years, the development of the Internet of Things (IoT) has prompted the search for nA-range current references that are simultaneously constrained to a small area and robust to process, voltage and temperature variations. Yet,…

Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V and 5V) are presented in this paper. Several PMOS and NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias…

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on…

Cryogenic CMOS technology (cryo-CMOS) offers a scalable solution for quantum device interface fabrication. Several previous works have studied the characterization of CMOS technology at cryogenic temperatures for various process nodes.…

Silicon spin qubits are among the most promising candidates for large scale quantum computers, due to their excellent coherence and compatibility with CMOS technology for upscaling. Advanced industrial CMOS process flows allow wafer-scale…

The control interface of a large-scale quantum computer will likely require electronic sub-systems that operate in close proximity to the qubits, at deep cryogenic temperatures. Here, we report the low-temperature performance of custom…

We report the design-technology co-optimization (DTCO) scheme to develop a 28-nm cryogenic CMOS (Cryo-CMOS) technology for high-performance computing (HPC). The precise adjustment of halo implants manages to compensate the threshold voltage…

This paper presents low power dissipation, low phase noise ring oscillators (ROs) based on Semiconductor Manufacturing International Corporation (SMIC) 0.18{\mu}m CMOS technology at liquid helium temperature (LHT). First, the…

The extremely low threshold voltage (Vth) of native MOSFETs (Vth~0V@300K) is conducive to the design of cryogenic circuits. Previous research on cryogenic MOSFETs mainly focused on the standard threshold voltage (SVT) and low threshold…

This brief presents a technique for compensating the temperature coefficient (TC) of a bandgap reference (BGR) using temperature characteristics of transistor's current gain \b{eta}. As a comparison, three BGR circuits built with Si BJTs…

We report on an industry-grade CMOS-compatible qubit fabrication approach using a CMOS pilot line, enabling a yield of functional devices reaching 92.8 %, with a resistance spread evaluated across the full wafer 200 mm diameter of 12.4 %…

Conventional CMOS technology operated at cryogenic conditions has recently attracted interest for its uses in low-noise electronics. We present one of the first characterizations of 180 nm CMOS technology at a temperature of 100 mK,…

On-chip thermometry at deep-cryogenic temperatures is vital in quantum computing applications to accurately quantify the effect of increased temperature on qubit performance. In this work, we present a sub-1 K temperature sensor in CMOS…