CMOS-compatible processing and room-temperature characterization on wafer-level for scalable quantum computing

We report on an industry-grade CMOS-compatible qubit fabrication approach using a CMOS pilot line, enabling a yield of functional devices reaching 92.8 %, with a resistance spread evaluated across the full wafer 200 mm diameter of 12.4 % and relaxation times (T1) approaching 80 us. Furthermore, we conducted a comprehensive analysis of wafer-scale room temperature (RT) characteristics collected from multiple wafers and fabrication runs, focusing on RT measurements and their correlation to low temperature qubit parameters. From defined test structures, an across-wafer Josephson junction (JJ) area variation of 10.1 % and oxide barrier variation of 7.2 % was calculated. Additionally, from the room-temperature JJ characterization the qubit frequency can be derived on wafer-level applying the Ambegaokar-Baratoff model before low temperature measurements. This sets the stage for pre-cooldown wafer-level JJ evaluation and sorting. In particular, such early-on device characterization and validation are crucial for increasing the fabrication yield and qubit frequency targeting, which currently represent major scaling challenges. Furthermore, it enables the fabrication of large multichip quantum systems in the future. Our analysis highlight the great potential of CMOS-compatible industry-style fabrication of superconducting qubits for scalable quantum computing in a foundry pilot line cleanroom.