English
Related papers

Related papers: Is RISC-V ready for High Performance Computing? An…

200 papers

The Sophon SG2042 is the world's first commodity 64-core RISC-V CPU for high performance workloads and an important question is whether the SG2042 has the potential to encourage the HPC community to embrace RISC-V. In this paper we…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-10-04 Nick Brown , Maurice Jamieson , Joseph Lee , Paul Wang

Whilst RISC-V has grown phenomenally quickly in embedded computing, it is yet to gain significant traction in High Performance Computing (HPC). However, as we move further into the exascale era, the flexibility offered by RISC-V has the…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-06-19 Nick Brown , Maurice Jamieson

Whilst RISC-V has become popular in fields such as embedded computing, it is yet to find mainstream success in High Performance Computing (HPC). However, the 64-core RISC-V Sophon SG2042 is a potential game changer as it provides a…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-02-17 Nick Brown , Christopher Day

Many RISC-V (RV) platforms and SoCs have been announced in recent years targeting the HPC sector, but only a few of them are commercially available and engineered to fit the HPC requirements. The Monte Cimone project targeted assessing…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-03-03 Emanuele Venieri , Simone Manoni , Gabriele Ceccolini , Giacomo Madella , Federico Ficarelli , Daniele Gregori , Daniele Cesarini , Luca Benini , Andrea Bartolini

The Monte Cimone project provides a RISC-V testbed for High-Performacne Computing cluster. This paper presents Monte Cimone v3 (MCv3), the third iteration of the Monte Cimone RISC-V HPC cluster, integrating the SOPHGO Sophon SG2044…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-05-29 Emanuele Venieri , Simone Manoni , Giacomo Madella , Federico Proverbio , Federico Ficarelli , Luca Benini , Andrea Bartolini

The recent exponential growth of Large Language Models (LLMs) has relied on GPU-based systems. However, CPUs are emerging as a flexible and lower-cost alternative, especially when targeting inference and reasoning workloads. RISC-V is…

Machine Learning · Computer Science 2025-03-25 Javier J. Poveda Rodrigo , Mohamed Amine Ahmdi , Alessio Burrello , Daniele Jahier Pagliari , Luca Benini

Gaussian processes are widely used in machine learning domains but remain computationally demanding, limiting their efficient scalability across emerging hardware platforms. The GPRat library addresses these challenges using the HPX…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-05-29 Alexander Strack , Patrick Diehl , Dirk Pflüger

The new open and royalty-free RISC-V ISA is attracting interest across the whole computing continuum, from microcontrollers to supercomputers. High-performance RISC-V processors and accelerators have been announced, but RISC-V-based HPC…

Rapid advancements in RISC-V hardware development shift the focus from low-level optimizations to higher-level parallelization. Recent RISC-V processors, such as the SOPHON SG2042, have 64 cores. RISC-V processors with core counts…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-06-11 Alexander Strack , Christopher Taylor , Dirk Pflüger

Heterogeneous, multicore SoC architectures are a critical component of today's computing landscape. However, supporting both increasing heterogeneity and multicore execution are significant design challenges. Meanwhile, the growing RISC-V…

Hardware Architecture · Computer Science 2022-06-07 Joseph Zuckerman , Paolo Mantovani , Davide Giri , Luca P. Carloni

The rapid progress and advancement in electronic chips technology provide a variety of new implementation options for system engineers. The choice varies between the flexible programs running on a general-purpose processor (GPP) and the…

Hardware Architecture · Computer Science 2019-04-11 Issam Damaj

Whilst the RISC-V Vector extension (RVV) has been ratified, at the time of writing both hardware implementations and open source software support are still limited for vectorisation on RISC-V. This is important because vectorisation is…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-04-21 Joseph K. L. Lee , Maurice Jamieson , Nick Brown , Ricardo Jesus

This paper presents a comprehensive analysis of the RISC-V instruction set architecture, focusing on its modular design, implementation challenges, and performance characteristics. We examine the RV32I base instruction set with extensions…

Hardware Architecture · Computer Science 2025-06-10 Priyanshu Yadav

The emergence of a new, open, and free instruction set architecture, RISC-V, has heralded a new era in microprocessor architectures. Starting with low-power, low-performance prototypes, the RISC-V community has a good chance of moving…

Performance · Computer Science 2023-09-06 Valentin Volokitin , Evgeny Kozinov , Valentina Kustikova , Alexey Liniov , Iosif Meyerov

Spiking Neural Networks (SNNs) have gained significant attention in edge computing due to their low power consumption and computational efficiency. However, existing implementations either use conventional System on Chip (SoC) architectures…

Hardware Architecture · Computer Science 2026-03-13 Kanishka Gunawardana , Sanka Peeris , Kavishka Rambukwella , Thamish Wanduragala , Saadia Jameel , Roshan Ragel , Isuru Nawinne

Vector architectures are gaining traction for highly efficient processing of data-parallel workloads, driven by all major ISAs (RISC-V, Arm, Intel), and boosted by landmark chips, like the Arm SVE-based Fujitsu A64FX, powering the TOP500…

Hardware Architecture · Computer Science 2025-01-10 Matteo Perotti , Matheus Cavalcante , Nils Wistoff , Renzo Andri , Lukas Cavigelli , Luca Benini

RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as…

Hardware Architecture · Computer Science 2020-12-30 Hiromu Miyazaki , Takuto Kanamori , Md Ashraful Islam , Kenji Kise

In the last decade, we have witnessed exponential growth in the complexity of control systems for safety-critical applications (automotive, robots, industrial automation) and their transition to heterogeneous mixed-criticality systems…

Hardware Architecture · Computer Science 2024-06-12 Michael Rogenmoser , Alessandro Ottaviano , Thomas Benz , Robert Balas , Matteo Perotti , Angelo Garofalo , Luca Benini

In recent years, interest in RISC-V computing architectures has moved from academic to mainstream, especially in the field of High Performance Computing where energy limitations are increasingly a concern. As of this year, the first single…

The last few years have seen the emergence of IoT processors: ultra-low power systems-on-chips (SoCs) combining lightweight and flexible micro-controller units (MCUs), often based on open-ISA RISC-V cores, with application-specific…

Systems and Control · Electrical Eng. & Systems 2022-01-21 Nazareno Bruschi , Germain Haugou , Giuseppe Tagliavini , Francesco Conti , Luca Benini , Davide Rossi
‹ Prev 1 2 3 10 Next ›