Related papers: STAMP-2.5D: Structural and Thermal Aware Methodolo…
A numerical modeling study based on 3D finite element method (FEM) simulation and 1D analytical solutions has been carried out to evaluate the capabilities of two ac methods for measuring in-plane thermal conductivity of thin film deposited…
Vision processing on traditional architectures is inefficient due to energy-expensive off-chip data movement. Many researchers advocate pushing processing close to the sensor to substantially reduce data movement. However, continuous…
The article is aimed to address a mutually boosting use of asymptotic analysis and machine learning, for fast stiffness design of configurations infilled with smoothly-varying graded microstructures. The discussion is conducted in the…
For beyond 2-D CMOS logic, various 3-D integration approaches specially transistor based 3-D integrations such as monolithic 3-D [1], Skybridge [2], SN3D [3] holds most promise. However, such 3D architectures within small form factor…
With the increasing prevalence of chiplet systems in high-performance computing applications, the number of design options has increased dramatically. Instead of chips defaulting to a single die design, now there are options for 2.5D and 3D…
High power density systems require efficient cooling to maintain their thermal performance. Despite this, as systems get larger and more complex, human practice and insight may not suffice to determine the desired thermal management system…
Thermal management of power electronics and Electronic Control Units is crucial in times of increasing power densities and limited assembly space. Electric and autonomous vehicles are a prominent application field. Thermal Interface…
3D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealing with emerging security challenges such as side channel attacks,…
To resolve the rising temperatures in 3.5D-ICs, a thermal-aware design flow becomes increasingly crucial, necessitating an accurate and efficient thermal simulation tool. However, previous tools struggle to handle the unique heterogeneous…
Advanced packaging and chiplet-based integration are increasingly adopted to build complex heterogeneous systems beyond the limits of monolithic scaling. While these architectures offer major benefits in terms of modularity, yield, and…
Accurate knowledge of temperatures in power semiconductor modules is crucial for proper thermal management of such devices. Precise prediction of temperatures allows to operate the system at the physical limit of the device avoiding…
The semiconductor industry is reaching a fascinating confluence in several evolutionary trends that will likely lead to a number of revolutionary changes in the design, implementation, scaling, and the use of computer systems. However,…
The increasing electricity use and reliance on intermittent renewable energy sources challenge power grid management during peak demand, making Demand Response programs and energy conservation measures essential. This research combines…
Fine-grained sparsity promises higher parametric capacity without proportional per-token compute, but often suffers from training instability, load balancing, and communication overhead. We introduce STEM (Scaling Transformers with…
This work introduces an electromagnetic metastructure based interconnect design that could address the critical need for electrical bandwidth and heat dissipation in high-speed, chiplet integration. We leverage silicon as the substrate for…
Thermal analysis is increasingly critical in modern integrated circuits, where non-uniform power dissipation and high transistor densities can cause rapid temperature spikes and reliability concerns. Traditional methods, such as FEM-based…
Chiplet-based systems, integrating various silicon dies manufactured at different integrated circuit technology nodes on a carrier interposer, have garnered significant attention in recent years due to their cost-effectiveness and…
We introduce Scan2Plan, a novel approach for accurate estimation of a floorplan from a 3D scan of the structural elements of indoor environments. The proposed method incorporates a two-stage approach where the initial stage clusters an…
Memory tiering systems seek cost-effective memory scaling by adding multiple tiers of memory. For maximum performance, frequently accessed (hot) data must be placed close to the host in faster tiers and infrequently accessed (cold) data can…
3D integrated circuit (3D-IC) technology gained acceptance due to the ability to achieve extremely high level of integration, where hundreds of ICs are stacked vertically. Such level of integration can result in local power dissipation of…