Related papers: Technical challenges designing a prototype common …
A prescription to calculate the minimum number of bits needed for binary strip detector readout is presented. This permits a systematic analysis of the readout efficiency relative to this theoretical minimum number of bits. Different level…
In this work novel results concerning Network-on-Chip-based turbo decoder architectures are presented. Stemming from previous publications, this work concentrates first on improving the throughput by exploiting adaptive-bandwidth reduction…
The upgrade of the LHCb experiment, scheduled for LHC Run-III, scheduled to start in 2021, will transform the experiment to a trigger-less system reading out the full detector at 40 MHz event rate. All data reduction algorithms will be…
The ALICE collaboration consolidated and completed the installation of current detectors during LS1 with the aim to accumulate 1 nb$^{-1}$ of Pb-Pb collisions during Run 2 corresponding to about 10 times the Run 1 integrated luminosity. In…
During the upcoming Runs 3 and 4 of the LHC, ALICE will take data at a peak Pb-Pb collision rate of 50 kHz. This will be made possible thanks to the upgrade of the main tracking detectors of the experiment, and with a new data processing…
As the one-chip integration of HW-modules designed by different companies becomes more and more popular reliability of a HW-design and evaluation of the timing behavior during the prototype stage are absolutely necessary. One way to…
With the steady increase in the precision of flavour physics measurements collected during LHC Run 2, the LHCb experiment requires simulated data samples of larger and larger sizes to study the detector response in detail. The simulation of…
Scaling Large Language Model (LLM) training relies on multi-dimensional parallelism, where High-Bandwidth Domains (HBDs) are critical for communication-intensive parallelism like Tensor Parallelism. However, existing HBD architectures face…
Following the Phase-II upgrade during Long Shutdown (LS3), the LHC aims to reach a peak instantaneous luminosity of $7.5\times 10^{34}$cm$^{-2}$s$^{-1}$, which corresponds to an average of around 200 inelastic proton-proton collisions per…
The ALICE experiment at the Large Hadron Collider (LHC) proposes major detector upgrades to fully exploit the increase of the luminosity of the LHC in RUN~3 and to extend the physics reach for rare probes at low transverse momentum. The…
The brain may adopt the strategy of lateral predictive coding (LPC) to construct optimal internal representations for salient features in input sensory signals, reducing the energetic cost of information transmission. Here we first consider…
In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. Because of its radiation hardness and cost effectiveness, the n-on-p silicon…
Sub-THz bands are promising high bandwidth and data rates, and in the recent years the device technologies made large progress and provided a multitude of transceiver, power amplifier (PA) and phased array devices supporting the frequency…
We develop a custom printed circuit board (PCB) for a low-power and high-speed accelerator of NP-Hard graph problems. The architecture implements an annealing-based computing paradigm using a network of nonlinear electronic oscillators…
Electron and photon triggers covering transverse energies from 5 GeV to several TeV are essential for signal selection in a wide variety of ATLAS physics analyses to study Standard Model processes and to search for new phenomena. Final…
Printed Circuit Board (PCB) schematic design plays an essential role in all areas of electronic industries. Unlike prior works that focus on digital or analog circuits alone, PCB design must handle heterogeneous digital, analog, and power…
Constant-power loads are notoriously known to destabilise power systems, such as DC microgrids, due to their negative incremental impedance. This paper equips distributed generation units with decentralised L1 adaptive controllers at the…
A second major upgrade of the LHCb experiment is necessary to allow full exploitation of the High Luminosity LHC for flavour physics. The new experiment will operate in Run 5 of the LHC at a luminosity up to $1.5\times…
This paper proposes and evaluates a novel architecture for a low-power Time-to-Digital Converter with high resolution, optimized for both integration in multichannel chips and high rate operation (40 Mconversion/s/channel). This converter…
The present dissertation describes design, qualification and operation of several electronic instrumentations for High Energy Particle Physics experiments (LHCb) and Neutrino Physics experiments (CUORE and CUPID). Starting from 2019, the…