Related papers: Technical challenges designing a prototype common …
The LHCb Upgrade II will fully exploit the flavour-physics opportunities of the HL-LHC, and study additional physics topics that take advantage of the forward acceptance of the LHCb spectrometer. The LHCb Upgrade I will begin operation in…
The first level trigger of the CMS experiment is comprised of custom electronics that process data from the electromagnetic and hadron calorimeters and three technologies of muon detectors in order to select the most interesting events from…
Training on edge devices poses several challenges as these devices are generally resource-constrained, especially in terms of power. State-of-the-art techniques at the device level reduce the GPU frequency to enforce power constraints,…
The physics programme of the LHCb experiment at the Large Hadron Collider requires an efficient and precise reconstruction of the particle collision vertices. The LHCb Upgrade detector relies on a fully software-based trigger with an online…
In Run 3 of the LHC the LHCb experiment faces very high data rates containing beauty and charm hadron decays. Thus the task of the trigger is not to select any beauty and charm events, but to select those containing decays interesting for…
The continual increase of cores on server-grade CPUs raises demands on memory systems, which are constrained by limited off-chip pin and data transfer rate scalability. As a result, high-end processors typically feature lower memory…
This paper presents a survey of architectural features among four generations of Intel server processors (Sandy Bridge, Ivy Bridge, Haswell, and Broad- well) with a focus on performance with floating point workloads. Starting on the core…
With the rapid development of network protocol, TCP/IP has been widely applied in various OS systems because of its advantages of high-speed network transmission and standardization. Furthermore, TCP/IP has the functions of retransmission…
A noise-tolerant data communications fabric has been developed to meet the real-time data acquisition and control requirements of fast feedback loops, machine protection systems, pulse-to-pulse sequencing, and machine-experiment…
The challenging conditions of the High-Luminosity LHC require tailored hardware designs for the trigger and data acquisition systems. The Apollo platform features a "Service Module" with a powerful system-on-module computer that provides…
High-performance computing (HPC) requires resilience techniques such as checkpointing in order to tolerate failures in supercomputers. As the number of nodes and memory in supercomputers keeps on increasing, the size of checkpoint data also…
This paper focuses on data structures for multi-core reachability, which is a key component in model checking algorithms and other verification methods. A cornerstone of an efficient solution is the storage of visited states. In related…
Matrix extensions have emerged as an essential feature in modern CPUs to address the surging demands of AI workloads. However, existing designs often incur substantial hardware and software design overhead. Tight coupling with the CPU…
Network switches and routers need to serve packet writes and reads at rates that challenge the most advanced memory technologies. As a result, scaling the switching rates is commonly done by parallelizing the packet I/Os using multiple…
In recent years, it has become increasingly common for high performance computers (HPC) to possess some level of heterogeneous architecture - typically in the form of GPU accelerators. In some machines these are isolated within a dedicated…
Superconducting Digital (SCD) technology offers significant potential for enhancing the performance of next generation large scale compute workloads. By leveraging advanced lithography and a 300 mm platform, SCD devices can reduce energy…
Power dissipation in integrated circuits is one of the major concerns to the research community, at the verge when more number of transistors are integrated on a single chip. The substantial source of power dissipation in sequential…
The CMS experiment has been designed with a two-level trigger system: the Level-1 Trigger, implemented on custom-designed electronics, and the High Level Trigger, a streamlined version of the CMS offline reconstruction software running on a…
In this paper, the design and the performance of two prototype detectors based on Micromegas technology with a pad readout geometry is discussed. In addition, two alternative implementations of a spark-resistent protection layer on top of…
Printed electronics have gained significant traction in recent years, presenting a viable path to integrating computing into everyday items, from disposable products to low-cost healthcare. However, the adoption of computing in these…