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Multiplication is an important arithmetic operation that is frequently encountered in microprocessing and digital signal processing applications, and multiplication is physically realized using a multiplier. This paper discusses the…

Hardware Architecture · Computer Science 2019-05-17 P Balasubramanian , D L Maskell

In this work faster unsigned multiplication has been achieved by using a combination of High Performance Multiplication [HPM] column reduction technique and implementing a N-bit multiplier using 4 N/2-bit multipliers (recursive…

Hardware Architecture · Computer Science 2011-10-20 V. Sreedeep , B. Ramkumar , Harish M Kittur

In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy…

Performance · Computer Science 2010-10-01 H G Rangaraju , U. Venugopal , K N Muralidhara , K B Raja

Memristive Processing In-Memory (PIM) is one of the promising techniques for overcoming the Von-Neumann bottleneck. Reduction of data transfer between processor and memory and data processing by memristors in data-intensive applications…

Emerging Technologies · Computer Science 2024-10-15 Seyed Erfan Fatemieh , Bahareh Bagheralmoosavi , Mohammad Reza Reshadinezhad

Multiplication is a basic arithmetic operation that is encountered in almost all general-purpose microprocessing and digital signal processing applications, and multiplication is physically realized using a multiplier. This paper discusses…

Hardware Architecture · Computer Science 2019-05-28 P Balasubramanian , D L Maskell , N E Mastorakis

There is a recent trend in artificial intelligence (AI) inference towards lower precision data formats down to 8 bits and less. As multiplication is the most complex operation in typical inference tasks, there is a large demand for…

Hardware Architecture · Computer Science 2024-05-06 Andreas Böttcher , Martin Kumm

In this work, we present a class of new designs for reversible binary and BCD adder circuits. The proposed designs are primarily optimized for the number of ancilla inputs and the number of garbage outputs and are designed for possible best…

Quantum Physics · Physics 2017-12-08 Himanshu Thapliyal , Nagarajan Ranganathan

A reversible logic has application in quantum computing. A reversible logic design needs resources such as ancilla and garbage qubits to reconfigure circuit functions or gate functions. The removal of garbage qubits and ancilla qubits are…

Quantum Physics · Physics 2016-08-04 Jayashree HV , Himanshu Thapliyal , Hamid R. Arabnia , V K Agrawal

Printed Electronics (PE) provide a flexible, cost-efficient alternative to silicon for implementing machine learning (ML) circuits, but their large feature sizes limit classifier complexity. Leveraging PE's low fabrication and NRE costs,…

Machine Learning · Computer Science 2025-09-22 Giorgos Armeniakos , Theodoros Mantzakidis , Dimitrios Soudris

Multiplier circuits play an important role in reversible computation, which is helpful in diverse areas such as low power CMOS design, optical computing, DNA computing and bioinformatics. Here we propose a new reversible multiplier circuit…

Quantum Physics · Physics 2009-07-21 Anindita Banerjee , Anirban Pathak

We present a novel set of reversible modular multipliers applicable to quantum computing, derived from three classical techniques: 1) traditional integer division, 2) Montgomery residue arithmetic, and 3) Barrett reduction. Each multiplier…

Quantum Physics · Physics 2018-01-04 Rich Rines , Isaac Chuang

Multiplication is an indispensable operation in most of digital signal processing systems. Recently, many systems need to execute different types of algorithms on a multiplier. Therefore, it needs complicated computation and large area…

Hardware Architecture · Computer Science 2019-07-23 Seungbum Baek

An integer adder for integers in the binary representation is one of the basic operations of any digital processor. For adding two integers of N bits each, the serial adder takes as many clock ticks. For achieving higher speeds, parallel…

Hardware Architecture · Computer Science 2019-03-26 Duggirala Meher Krishna , Duggirala Ravi

Quantum computers require quantum processors. An important part of the processor of any computer is the arithmetic unit, which performs binary addition, subtraction, division and multiplication, however multiplication can be performed using…

Quantum Physics · Physics 2018-11-14 Rasha Montaser , Ahmed Younes , Mahmoud Abdel-Aty

Electronic devices primarily aim to offer low power consumption, high speed, and a compact area. The performance of very large-scale integration (VLSI) devices is influenced by arithmetic operations, where multiplication is a crucial…

Hardware Architecture · Computer Science 2025-06-16 Ali Ranjbar , Elham Esmaeili , Roghayeh Rafieisangari , Nabiollah Shiri

Wallace tree multipliers are a parallel digital multiplier architecture designed to minimize the worst-case time complexity of the circuit depth relative to the input size [1]. In particular, it seeks to perform long multiplication in the…

Hardware Architecture · Computer Science 2025-09-12 Ayan Biswas , Jimmy Jin

In-memory computing is a promising alternative to traditional computer designs, as it helps overcome performance limits caused by the separation of memory and processing units. However, many current approaches struggle with unreliable…

In the last decades, great achievements have been made in the development of computing machines. However, due to exponential growth of transistor density and in particular due to tremendously increasing power consumption, researchers expect…

Emerging Technologies · Computer Science 2014-07-03 Piyush Gautam

We propose and analyze a compact and non-volatile nanomagnetic (all-spin) non-binary matrix multiplier performing the multiply-and-accumulate (MAC) operation using two magnetic tunnel junctions - one activated by strain to act as the…

Emerging Technologies · Computer Science 2023-02-28 Rahnuma Rahman , Supriyo Bandyopadhyay

We present a pipelined multiplier with reduced activities and minimized interconnect based on online digit-serial arithmetic. The working precision has been truncated such that $p<n$ bits are used to compute $n$ bits product, resulting in…

Hardware Architecture · Computer Science 2022-04-21 Muhammad Usman , Jeong-A Lee , Milos D. Ercegovac
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