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This work presents a method to maximize power-efficiency of fixed point multiplier units by decomposing them into sub-components. First, an encoder block converts the operands from a two's complement to a sign magnitude representation,…

Neural and Evolutionary Computing · Computer Science 2025-07-25 Felix Arnold , Maxence Bouvier , Ryan Amaudruz , Renzo Andri , Lukas Cavigelli

In this paper, new schemes for a squarer, multiplier and divider of complex numbers are proposed. Traditional structural solutions for each of these operations require the presence some number of general-purpose binary multipliers. The…

Hardware Architecture · Computer Science 2017-05-23 Aleksandr Cariow , Galina Cariowa

Multiplication is indispensable and is one of the core operations in many modern applications including signal processing and neural networks. Conventional right-to-left (RL) multiplier extensively contributes to the power consumption, area…

Hardware Architecture · Computer Science 2023-05-17 Muhammad Usman , Milos Ercegovac , Jeong-A Lee

Binary logic and devices have been in used since inception with advancement and technology and millennium gate design era. The development in binary logic has become tedious and cumbersome. Multivalued logic enables significant more…

Other Computer Science · Computer Science 2013-10-23 Hitesh Gupta , Dr. S. C. Jain

Vector multiplication is a fundamental operation for AI acceleration, responsible for over 85% of computational load in convolution tasks. While essential, these operations are primary drivers of area, power, and delay in modern datapath…

Hardware Architecture · Computer Science 2026-02-24 Md Rownak Hossain Chowdhury , Mostafizur Rahman

All-optical devices are essential for next generation ultrafast, ultralow-power and ultrahigh bandwidth information processing systems. Silicon microring resonators (SiMRR) provide a versatile platform for all-optical switching and…

Optics · Physics 2022-10-11 Aayushman Ghosh , Sayan Sarkar , Sukhdev Roy

Wristwatches have been a common fashion accessory addition for several people. However, the concept of using a seven-segment digital display or sometimes, even an analog indicator hasn't changed for a number of years. This project aims to…

Other Computer Science · Computer Science 2021-02-15 Jacob John

A multiplier, as a key component in many different applications, is a time-consuming, energy-intensive computation block. Approximate computing is a practical design paradigm that attempts to improve hardware efficacy while keeping…

Hardware Architecture · Computer Science 2023-08-16 Fereshteh Karimi , Reza Faghih Mirzaee , Ali Fakeri-Tabrizi , Arman Roohi

The technique for hardware multiplication based upon Fourier transformation has been introduced. The technique has the highest efficiency on multiplication units with up to 8 bit range. Each multiplication unit is realized on base of the…

Hardware Architecture · Computer Science 2016-11-17 Danila Gorodecky

Binary logic programs can be obtained from ordinary logic programs by a binarizing transformation. In most cases, binary programs obtained this way are less efficient than the original programs. (Demoen, 1992) showed an interesting example…

Programming Languages · Computer Science 2007-05-23 Jan Hruza , Petr Stepanek

Fast binary compressors are the main components of many basic digital calculation units. In this paper, a high-speed (7,2) compressor with a fast carry-generation logic is proposed. The carry-generation logic is based on the sorting…

Hardware Architecture · Computer Science 2023-09-08 Wenbo Guo

In the recent era, Reversible computing is a growing field having applications in nanotechnology, optical information processing, quantum networks etc. In this paper, the authors show the design of a cost effective reversible programmable…

Other Computer Science · Computer Science 2012-04-26 Pradeep Singla , Naveen Kr. Malik

Fast combinational multipliers with large bit widths can occupy significant silicon area, which also drives up power consumption. Area can be reduced through resource sharing (i.e., folding) at the expense of lower throughput, which is…

Hardware Architecture · Computer Science 2025-09-03 Ahmad Houraniah , H. Fatih Ugurdag , C. Emre Dedeagac

In cryptographic algorithms, the constants to be multiplied by a variable can be very large due to security requirements. Thus, the hardware complexity of such algorithms heavily depends on the design architecture handling large constants.…

Cryptography and Security · Computer Science 2023-09-13 Levent Aksoy , Debapriya Basu Roy , Malik Imran , Samuel Pagliarini

Binary embedding of high-dimensional data requires long codes to preserve the discriminative power of the input space. Traditional binary coding methods often suffer from very high computation and storage costs in such a scenario. To…

Machine Learning · Statistics 2014-05-14 Felix X. Yu , Sanjiv Kumar , Yunchao Gong , Shih-Fu Chang

In today's world everyday a new technology which is faster, smaller and more complex than its predecessor is being developed. The increased number of transistors packed onto a chip of a conventional system results in increased power…

Hardware Architecture · Computer Science 2013-06-11 Aakash Gupta , Pradeep Singla , Jitendra Gupta , Nitin Maheshwari

As transistor dimensions continue to shrink, binary devices are rapidly approaching their fundamental limits in power density. In response, multi-valued systems have attracted significant attention due to their enhanced information density.…

Molecular Networks · Quantitative Biology 2026-04-28 Enqiang Zhu , Peize Qiu , Xianhang Luo , Chanjuan Liu , Jin Xu

In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not…

Hardware Architecture · Computer Science 2007-05-23 Himanshu Thapliyal , M. B Srinivas

Multiplication is a fundamental operation in many applications, and multipliers are widely adopted in various circuits. However, optimizing multipliers is challenging due to the extensive design space. In this paper, we propose a multiplier…

Hardware Architecture · Computer Science 2024-12-30 Dongsheng Zuo , Jiadong Zhu , Yikang Ouyang , Yuzhe Ma

Matrix-matrix multiplication is a key computational kernel for numerous applications in science and engineering, with ample parallelism and data locality that lends itself well to high-performance implementations. Many matrix…

Hardware Architecture · Computer Science 2019-06-12 Yaman Umuroglu , Davide Conficconi , Lahiru Rasnayake , Thomas B. Preusser , Magnus Sjalander