Multipliers: comparison of Fourier transformation based method and Synopsys design technique for up to 32 bits inputs in regular and saturation arithmetics
Abstract
The technique for hardware multiplication based upon Fourier transformation has been introduced. The technique has the highest efficiency on multiplication units with up to 8 bit range. Each multiplication unit is realized on base of the minimized Boolean functions. Experimental data showed that this technique the multiplication process speed up to 20% higher for 2-8 bit range of input operands and up to 3% higher for 8-32 bit range of input operands than analogues designed by Synopsys technique.
Keywords
Cite
@article{arxiv.1611.05415,
title = {Multipliers: comparison of Fourier transformation based method and Synopsys design technique for up to 32 bits inputs in regular and saturation arithmetics},
author = {Danila Gorodecky},
journal= {arXiv preprint arXiv:1611.05415},
year = {2016}
}
Comments
Proceedings of the 12th International Workshop on Boolean Problems, Freiberg, Germany, Sept. 22-23, 2016. Edited by B. Steinbach. Freiberg University of Mining and Technology. P. 145-150. Changed title from "Multipliers design technique based disjunctive normal form minimizationa and Fourier transformation"; fixed some inaccuracies