New Design of Reversible Full Adder/Subtractor using $R$ gate
Abstract
Quantum computers require quantum processors. An important part of the processor of any computer is the arithmetic unit, which performs binary addition, subtraction, division and multiplication, however multiplication can be performed using repeated addition, while division can be performed using repeated subtraction. In this paper we present two designs using the reversible gate to perform the quantum half adder/ subtractor and the quantum full adder/subtractor. The proposed half adder/subtractor design can be used to perform different logical operations, such as , , , , and copy of basis. The proposed design is compared with the other previous designs in terms of the number of gates used, the number of constant bits, the garbage bits, the quantum cost and the delay. The proposed designs are implemented and tested using GAP software.
Cite
@article{arxiv.1708.00306,
title = {New Design of Reversible Full Adder/Subtractor using $R$ gate},
author = {Rasha Montaser and Ahmed Younes and Mahmoud Abdel-Aty},
journal= {arXiv preprint arXiv:1708.00306},
year = {2018}
}