Related papers: Preliminary Design of a General Electronics Platfo…
Conventional analog-to-digital converters (ADCs) fail to capture high-dynamic-range (HDR) signals due to clipping. Modulo ADCs circumvent this limitation by folding the input prior to quantization and algorithmically reconstructing the…
In this paper we develop the first fine-grained rounding error analysis of finite element (FE) cell kernels and assembly. The theory includes mixed-precision implementations and accounts for hardware-acceleration via matrix multiplication…
The multi-stage method of laser wakefield acceleration (LWFA) presents a promising approach for developing stable, full-optical, high-energy electron accelerators. By segmenting the acceleration process into several booster stages, each…
Wakefield accelerators are under development in many laboratories worldwide. They bring the promise of a high accelerating gradient, orders of magnitude higher than current machines. The reduction in the overall length of the accelerators…
We present a method of embedding a Monolithic Active Pixel Sensor (MAPS) into a flexible printed circuit board (FPC) and its interconnection by means of through-hole copper plating. The resulting assembly, baptised "MAPS foil", is a…
In this chapter, we aim to explore an in-depth exploration of the specialized hardware accelerators designed to enhance Artificial Intelligence (AI) applications, focusing on their necessity, development, and impact on the field of AI. It…
In this paper, an analytical framework for evaluating the performance of scalable cell-free massive MIMO (SCF-mMIMO) systems in which all user equipments (UEs) and access points (APs) employ finite resolution digital-to-analog converters…
The development of complex functional materials poses a multi-objective optimization problem in a large multidimensional parameter space. Solving it requires reproducible, user independent laboratory work and intelligent preselection of…
This work introduces MICSim, an open-source, pre-circuit simulator designed for early-stage evaluation of chip-level software performance and hardware overhead of mixed-signal compute-in-memory (CIM) accelerators. MICSim features a modular…
The ALICE Muon Trigger is currently yielded by a detector currently composed of 72 Bakelite single-gap Resistive Plate Chambers operated in maxi-avalanche mode, arranged in four 5.5x6.5 m2 detection planes. In order to meet the requirements…
As the increasing complexity of Neural Network(NN) models leads to high demands for computation, AMD introduces a heterogeneous programmable system-on-chip (SoC), i.e., Versal ACAP architectures featured with programmable logic (PL), CPUs,…
A new type of Time Projection Chamber (TPC) has been proposed for the upgrade of the ALICE (A Large Ion Collider Experiment at CERN) so as to cater to the high luminosity environment expected at the Large Hadron Collider (LHC) facility in…
Field-Programmable Gate Arrays (FPGAs) are widely used in the central signal processing design of the Square Kilometre Array (SKA) as acceleration hardware. The frequency domain acceleration search (FDAS) module is an important part of the…
Flexible Electronics (FE) offer distinct advantages, including mechanical flexibility and low process temperatures, enabling extremely low-cost production. To address the demands of applications such as smart sensors and wearables, flexible…
Transformer uses GPU as the initial design platform, but GPU can only perform limited hardware customization. Although FPGA has strong customization ability, the design solution space is huge and the design difficulty is high. Versal ACAP…
The upgrade of the Resistive Plate Chamber (RPC) detector, in order to increase the detector rate capability and to be able to work efficiently in high rate environment, consists in the reduction of the operating voltage along with the…
Superconducting Radio Frequency (SRF) cavities are used in modern accelerators to efficiently accelerate particles. When cavity is supplied with pulsed RF field it undergoes a mechanical strain due to the Lorentz force. The resulting…
In this work, we propose an architecture and methodology to design hardware/software systems for high-performance embedded computing on FPGA. The hardware side is based on a many-core architecture whose design is generated automatically…
It is proposed to place the arcs of an SLC-type facility inside the tunnel of a Future Circular Collider (FCC). Accelerated by a linear accelerator (linac), electron and positron beams would traverse the bending arcs in opposite directions…
Modern SoC-FPGA that consists of FPGA with embedded ARM cores is being popularized as an embedded vision system platform. However, the design approach of SoC-FPGA applications still follows traditional hardware-software separate workflow,…