Related papers: Performance of FPGA controller in ISAC-1 accelerat…

The Low-Level RF (LLRF) control circuits of linear accelerators (LINACs) are conventionally realized with heterodyne based architectures, which have analog RF mixers for up and down conversion with discrete data converters. We have…

The ISIS synchrotron at the Rutherford Appleton Laboratory in the UK now routinely uses a dual harmonic RF system to accelerate beam currents in excess of 230uA to run two target stations simultaneously. The acceleration in the ISIS…

The low level rf (LLRF) control system for the rapid cycling synchrotron (RCS) of the Japan Proton Accelerator Research Complex (J-PARC) started its operation in 2007. The key functions of the LLRF control system are the dual harmonic auto…

Normal conducting linear particle accelerators consist of multiple rf stations with accelerating structure cavities. Low-level rf (LLRF) systems are employed to set the phase and amplitude of the field in the accelerating structure, and to…

The ISIS buncher system at TRIUMF operates at frequencies of 23MHz, 46MHz, and 4.6MHz. The 23MHz and 46MHz signals drive two buncher cavities, while the 4.6MHz signal drives the 5:1 selector. The previous analog-digital hybrid system has…

A compact low-level RF (LLRF) control system based on RF system-on-chip (RFSoC) technology has been designed for the Advanced Concept Compact Electron Linear-accelerator (ACCEL) program, which has challenging requirements in both RF…

LCLS-II is currently in its commissioning phase at SLAC. It is an X-ray FEL driven by a CW superconducting LINAC. The beam injector plays a crucial role in the overall performance of the accelerator, and is critical to the final electron…

The first generation Low-Level radio frequency(LLRF) control system independently developed by IMPCAS, the operating frequency is 162.5MHz for China ADS, which consists of superconducting cavity amplitude stability control, phase stability…

There are many stages in the LLRF and RF system development process for any new accelerator that can take advantage of hardware emulation of the high-power RF system and RF cavities. LLRF development, bench testing, control system…

Low Level RF (LLRF) control systems of linear accelerators (LINACs) are typically implemented with heterodyne based architectures, which have complex analog RF mixers for up and down conversion. The Gen 3 Radio Frequency System-on-Chip…

Currently ALS is undergoing an upgrade to ALSU to produce 100 times brighter soft X-ray light. The LLRF system for Accumulator Ring (AR) is composed of two identical LLRF stations, for driving RF amplifiers. The closed loop RF amplitude and…

The FLASH L-band (1.3 GHz) superconducting accelerator facility at DESY has a Low Level RF (LLRF) system that is similar to that envisioned for ILC. This system has extensive monitoring capability and was used to gather performance data…

Superconducting cavities (SRF) are widely used in new generation particle accelerators, increasing the requirements and specifications for new designs. The LLRF control system, including the detuning control due to mechanical perturbations,…

This work describes the LLRF and control system in use for a novel accelerator structure developed for a compact design operating in C-band developed by SLAC, with collaboration from RadiaBeam and RadiaSoft. This design is a pulsed…

A LLRF control and data acquisition system for the 8-cavity cryomodule1 at the ILCTA has been implemented using three 33-channel ADC boards in a VXI mainframe. One card each is dedicated to the cavity probes for vector control, forward…

PIP-II is a superconducting linac that is in the initial acceleration chain for the Fermilab accelerator complex. The RF system consists of a warm front-end with an RFQ and buncher cavities along with 25 superconducting cryo-modules…

The FLASH L-band (1.3 GHz) superconducting accelerator facility at DESY has a Low Level RF (LLRF) system that is similar to that envisioned for ILC. This system has extensive monitoring capability and was used to gather performance data…

A 20 GHz LLRF system is being built using a two-board(RF Front End + ADC/DAC/FPGA) architecture. The RF Front End provides 8 down-converting channels and 3 up-converting channels (5.5-20 GHz RF to 0.05-3 GHz IF). Separate, phase locked,…

Synchronous reference frame phase-looked loop (SRF-PLL) techniques are widely used for interfacing and control applications in the power systems and energy conversion at large. Since a PLL system synchronizes its output with an exogenous…

Waveform feature is one of the requirements for the FRIB LLRF controllers. It is desired that the LLRF con-trollers store the internal data (e.g. the amplitude and phase information of forward/reverse/cavity signals) for at least one second…