Related papers: The interface states in gate-all-around transistor…
Recently, short channel effects (SCE) and power consumption dissipation problems pose big challenges which need imperative actions to be taken to deal with for field effect transistor to further scale down as semiconductor technology enters…
As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor…
The influence of interface roughness scattering (IRS) on the performances of silicon nanowire field-effect transistors (NWFETs) is numerically investigated using a full 3D quantum transport simulator based on the atomistic sp3d5s*…
Gate-All-Around Field-Effect Transistors (GAAFETs), now entering high-volume production as successors to fin field-effect transistor technology, are enabling continued scaling and enhanced performance in advanced semiconductor nodes.…
To improve transistor density and electronic performance, next-generation semiconductor devices are adopting three-dimensional architectures and feature sizes down to the few-nm regime, which require atomic-scale metrology to identify and…
In this work, quantum ballistic simulation study of a III-V tri-gate MOSFET has been presented. At the same time, effects of device parameter variation on ballistic, subthrshold and short channel performance is observed and presented. The…
Quantum computation and quantum simulation require a versatile gate set to optimize circuit compilation for practical applications. However, existing platforms are often limited to specific gate types or rely on parametric couplers to…
High performance InGaAs gate-all-around (GAA) nanowire MOSFETs with channel length (Lch) down to 20nm have been fabricated by integrating a higher-k LaAlO3-based gate stack with an equivalent oxide thickness of 1.2nm. It is found that…
Quantization in the inversion layer and phase coherent transport are anticipated to have significant impact on device performance in 'ballistic' nanoscale transistors. While the role of some quantum effects have been analyzed qualitatively…
High-fidelity flow simulations are indispensable when analyzing systems exhibiting multiphase flow phenomena. The accuracy of multiphase flow simulations is strongly contingent upon the finest mesh resolution used to represent the…
High-connectivity circuits are a major roadblock for current quantum hardware. We propose a hybrid classical-quantum algorithm to simulate such circuits without swap-gate ladders. As main technical tool, we introduce…
An unresolved challenge facing electronics at a few-nm scale is that resistive channels start leaking due to quantum tunneling. This affects the performance of nanoscale transistors, with single-molecule devices displaying particularly low…
The potential barrier between source and gate in HEMTs and between source and channel in MOSFET controls the current output and the velocity injection of electrons in the channel [1], [2]. In non self aligned structures the electric field…
We explore nanoribbons from topological two-dimensional stanene as channel material in tunnel field effect transistors. This novel technological option offers the possibility to build pure one-dimensional (1D) channel devices (comprised of…
Topological insulator field-effect transistors (TIFETs) built on 2-D quantum spin Hall insulators are being considered as advanced logic transistors due to their potentially superior performance originating from the dissipationless edge…
The first inversion-mode gate-all-around (GAA) III-V MOSFETs are experimentally demonstrated with a high mobility In0.53Ga0.47As channel and atomic-layer-deposited (ALD) Al2O3/WN gate stacks by a top-down approach. A well-controlled InGaAs…
We develop a robust and versatile platform to define nanostructures at oxide interfaces via patterned top gates. Using LaAlO$_3$/SrTiO$_3$ as a model system, we demonstrate controllable electrostatic confinement of electrons to nanoscale…
A simulation methodology for ultra-scaled InAs quantum well field effect transistors (QWFETs) is presented and used to provide design guidelines and a path to improve device performance. A multiscale modeling approach is adopted, where…
A key requirement to perform simulations of large quantum systems on near-term quantum hardware is the design of quantum algorithms with short circuit depth that finish within the available coherence time. A way to stay within the limits of…
The latest field-effect transistors are entering the regime where quantum effects within the conduction channel can play a significant role because of the increasingly reduced dimensions. We investigate the effects of quantized states in…