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This paper presents a simulation platform, namely CIMulator, for quantifying the efficacy of various synaptic devices in neuromorphic accelerators for different neural network architectures. Nonvolatile memory devices, such as resistive…

Analog in-memory computing (AIMC) cores offers significant performance and energy benefits for neural network inference with respect to digital logic (e.g., CPUs). AIMCs accelerate matrix-vector multiplications, which dominate these…

Massive emerging applications are driving demand for the ubiquitous deployment of computing power today. This trend not only spurs the recent popularity of the \emph{Computing and Network Convergence} (CNC), but also introduces an urgent…

Artificial Intelligence · Computer Science 2023-08-08 Zicong Hong , Xiaoyu Qiu , Jian Lin , Wuhui Chen , Yue Yu , Hui Wang , Song Guo , Wen Gao

Due to amount of data involved in emerging deep learning and big data applications, operations related to data movement have quickly become the bottleneck. Data-centric computing (DCC), as enabled by processing-in-memory (PIM) and…

Hardware Architecture · Computer Science 2020-09-22 Kamil Khan , Sudeep Pasricha , Ryan Gary Kim

The conventional approach of moving data to the CPU for computation has become a significant performance bottleneck for emerging scale-out data-intensive applications due to their limited data reuse. At the same time, the advancement in 3D…

The computing wall and data movement challenges of deep neural networks (DNNs) have exposed the limitations of conventional CMOS-based DNN accelerators. Furthermore, the deep structure and large model size will make DNNs prohibitive to…

Signal Processing · Electrical Eng. & Systems 2019-12-12 Geng Yuan , Xiaolong Ma , Sheng Lin , Zhengang Li , Caiwen Ding

Computing in-memory (CiM) has emerged as an attractive technique to mitigate the von-Neumann bottleneck. Current digital CiM approaches for in-memory operands are based on multi-wordline assertion for computing bit-wise Boolean functions…

Hardware Architecture · Computer Science 2022-01-25 Akul Malhotra , Atanu K. Saha , Chunguang Wang , Sumeet K. Gupta

As an emerging type of AI computing accelerator, SRAM Computing-In-Memory (CIM) accelerators feature high energy efficiency and throughput. However, various CIM designs and under-explored mapping strategies impede the full exploration of…

Hardware Architecture · Computer Science 2026-01-27 Jinwu Chen , Yuhui Shi , He Wang , Zhe Jiang , Jun Yang , Xin Si , Zhenhua Zhu

Intermittent computing systems operate by relying only on harvested energy accumulated in their tiny energy reservoirs, typically capacitors. An intermittent device dies due to a power failure when there is no energy in its capacitor and…

Hardware Architecture · Computer Science 2022-02-17 Simone Ruffini , Luca Caronti , Kasım Sinan Yıldırım , Davide Brunelli

In-Memory Computing (IMC) introduces a new paradigm of computation that offers high efficiency in terms of latency and power consumption for AI accelerators. However, the non-idealities and defects of emerging technologies used in advanced…

Computing-in-Memory (CIM) macros have gained popularity for deep learning acceleration due to their highly parallel computation and low power consumption. However, limited macro size and ADC precision introduce throughput and accuracy…

Hardware Architecture · Computer Science 2026-05-01 Ming-Han Lin , Tian-Sheuan Chang

Spiking Neural Networks (SNNs) are bio-plausible models that hold great potential for realizing energy-efficient implementations of sequential tasks on resource-constrained edge devices. However, commercial edge platforms based on standard…

Neural and Evolutionary Computing · Computer Science 2023-09-26 Marco Paul E. Apolinario , Adarsh Kumar Kosta , Utkarsh Saxena , Kaushik Roy

The emerging hybrid DRAM-NVM architecture is challenging the existing memory management mechanism in operating system. In this paper, we introduce memos, which can schedule memory resources over the entire memory hierarchy including cache,…

Operating Systems · Computer Science 2017-03-23 Lei Liu , Mengyao Xie , Hao Yang

The demand for computation resources and energy efficiency of Convolutional Neural Networks (CNN) applications requires a new paradigm to overcome the "Memory Wall". Analog In-Memory Computing (AIMC) is a promising paradigm since it…

Distributed, Parallel, and Cluster Computing · Computer Science 2022-11-24 Nazareno Bruschi , Giuseppe Tagliavini , Angelo Garofalo , Francesco Conti , Irem Boybat , Luca Benini , Davide Rossi

Biologically-inspired computing models have made significant progress in recent years, but the conventional von Neumann architecture is inefficient for the large-scale matrix operations and massive parallelism required by these models. This…

Hardware Architecture · Computer Science 2025-09-23 Siqing Fu , Lizhou Wu , Tiejun Li , Chunyuan Zhang , Jianmin Zhang , Sheng Ma

Neuro-symbolic artificial intelligence (AI) excels at learning from noisy and generalized patterns, conducting logical inferences, and providing interpretable reasoning. Comprising a 'neuro' component for feature extraction and a 'symbolic'…

Non-volatile memory (NVM) crossbars have been identified as a promising technology, for accelerating important machine learning operations, with matrix-vector multiplication being a key example. Binary neural networks (BNNs) are especially…

Emerging Technologies · Computer Science 2023-08-14 Ruirong Huang , Zichao Yue , Caroline Huang , Janarbek Matai , Zhiru Zhang

Main memories play an important role in overall energy consumption of embedded systems. Using conventional memory technologies in future designs in nanoscale era causes a drastic increase in leakage power consumption and temperature-related…

Hardware Architecture · Computer Science 2019-12-16 Salman Onsori , Arghavan Asad , Kaamran Raahemifar , Mahmood Fathy

Hashmaps are widely utilized data structures in many applications to perform a probe on key-value pairs. However, their performance tends to degrade with the increase in the dataset size, which leads to expensive off-chip memory accesses to…

Hardware Architecture · Computer Science 2023-07-03 Akhil Shekar , Morteza Baradaran , Sabiha Tajdari , Kevin Skadron

Edge deployment of low-batch large language models (LLMs) faces critical memory bandwidth bottlenecks when executing memory-intensive general matrix-vector multiplications (GEMV) operations. While digital processing-in-memory (PIM)…

Hardware Architecture · Computer Science 2026-01-21 Ye Lin , Chao Fang , Xiaoyong Song , Qi Wu , Anying Jiang , Yichuan Bai , Li Du
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