Related papers: Low-Latency Analog-to-Analog Signal Processing usi…

This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was published in HPCA 2015. The key goal of AL-DRAM is to exploit the extra margin that is built into the DRAM timing parameters to reduce DRAM latency. The key…

One of the major challenges for the engineering of wireless sensing systems is to improve the software abstractions and frameworks that are available to programmers while ensuring system reliability and efficiency. The distributed systems…

Simulations of optical quantum systems are essential for the development of quantum technologies. However, these simulations are often computationally intensive, especially when repeated evaluations are required for data fitting, parameter…

We designed and implemented a deep learning based RF signal classifier on the Field Programmable Gate Array (FPGA) of an embedded software-defined radio platform, DeepRadio, that classifies the signals received through the RF front end to…

To foster the adoption of active disturbance rejection control (ADRC) and support its deployment even on low-cost embedded systems, this article introduces the most efficient implementation of linear discrete-time ADRC to date. While…

The proliferation of high-throughput sequencing machines ensures rapid generation of up to billions of short nucleotide fragments in a short period of time. This massive amount of sequence data can quickly overwhelm today's storage and…

Transformer-based speech enhancement models yield impressive results. However, their heterogeneous and complex structure restricts model compression potential, resulting in greater complexity and reduced hardware efficiency. Additionally,…

We present and evaluate the ExaNeSt Prototype, a liquid-cooled rack prototype consisting of 256 Xilinx ZU9EG MPSoCs, 4 TBytes of DRAM, 16 TBytes of SSD, and configurable interconnection 10-Gbps hardware. We developed this testbed in…

Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations…

This paper presents the designs of asynchronous early output dual-bit full adders without and with redundant logic (implicit) corresponding to homogeneous and heterogeneous delay-insensitive data encoding. For homogeneous delay-insensitive…

Radio-frequency interference is a growing concern as wireless technology advances, with potentially life-threatening consequences like interference between radar altimeters and 5G cellular networks. Mobile transceivers mix signals with…

Spiking Neural Networks (SNNs) are bio-plausible models that hold great potential for realizing energy-efficient implementations of sequential tasks on resource-constrained edge devices. However, commercial edge platforms based on standard…

The long-range and low energy consumption requirements in Internet of Things (IoT) applications have led to a new wireless communication technology known as Low Power Wide Area Network (LPWANs). In recent years, the Long Range (LoRa)…

In-situ LLM inference on end-user devices has gained significant interest due to its privacy benefits and reduced dependency on external infrastructure. However, as the decoding process is memory-bandwidth-bound, the diverse processing…

This paper reports an implementation of the PHY specifications of the IEEE 802.15.4 standard for the frequency band 868 915 MHz on a Software Defined Radio (SDR) platform. This standard is defined for low power, low data rate and low cost…

Packet processing on Linux can be slow due to its complex network stack. To solve this problem, there are two main solutions: eXpress Data Path (XDP) and Data Plane Development Kit (DPDK). XDP and the AF XDP socket offer full…

This work demonstrates the first non-reciprocal network based on switched low-loss acoustic delay lines. The 4-port circulator is built upon a recently reported frequency-independent, programmable, non-reciprocal framework based on switched…

Data center interconnects (DCIs) will have to support throughputs of 400 Gbps or more per wavelength in the near future. To achieve such high data rates, coherent modulation and detection is used, which conventionally requires high-speed…

This thesis develops signal-processing algorithms and implementation schemes under constraints of minimal parallelism and memory space, with the goal of improving energy efficiency of low-power computing hardware. We propose (i) a…

We present a power efficient clock-less fully asynchronous bit-serial Low Voltage Differential Signaling (LVDS) link with event-driven instant wake-up and self-sleep features, optimized for high speed inter-chip communication of…