Related papers: Scaled indium oxide transistors fabricated using a…
Ultra-thin (UT) oxide semiconductors are promising candidates for back-end-of-line (BEOL) compatible transistors and monolithic three-dimensional integration. Experimentally, UT indium oxide (In$_2$O$_3$) field-effect transistors (FETs)…
We demonstrate a gate dielectric engineering approach leveraging an ultrathin, atomic layer deposited (ALD) silicon oxide interfacial layer (SiL) between the amorphous oxide semiconductor (AOS) channel and the high-k gate dielectric. SiL…
Guided by a comprehensive analysis of accumulation mode transistor physics and oxide semiconductor materials properties, we demonstrate an innovative oxide semiconductor transistor structure and process flow that break the constraint…
The radiation response of a 0.25 um silicon-on-sapphire CMOS technology is characterized at the transistor and circuit levels utilizing both standard and enclosed layout devices. Device-level characterization showed threshold voltage change…
As silicon transistors scale toward future technology nodes, three-dimensional architectures -- including gate-all-around (GAA) nanoribbon and complementary field-effect transistors (CFETs) -- require channel widths in the tens of…
This article is present the effected oxide capacitor in CMOS structure of integrated circuit level 5 micrometer technology. It has designed and basic structure of MOS diode. It establish with aluminum metallization layer by sputtering…
GaSb/InAs heterojunction tunnel field-effect transistors are strong candidates in building future low-power integrated circuits, as they could provide both steep subthreshold swing and large ON-state current ($I_{\rm{ON}}$). However, at…
3D NAND enables continuous NAND density and cost scaling beyond conventional 2D NAND. However, its poly-Si channel suffers from low mobility, large device variations, and instability caused by grain boundaries. Here, we overcome these…
Organic semiconductors are usually not thought to show outstanding performance in highly-integrated, sub 100 nm transistors. Consequently, single-crystalline materials such as SWCNTs, MoS2 or inorganic semiconductors are the material of…
Resistive switching devices herald a transformative technology for memory and computation, offering considerable advantages in performance and energy efficiency. Here we employ a simple and scalable material system of conductive oxide…
Paper is the ideal substrate for the development of flexible and environmentally sustainable ubiquitous electronic systems, which, combined with two-dimensional materials, could be exploited in many Internet-of-Things applications, ranging…
The main promise of tunnel FETs (TFETs) is to enable supply voltage ($V_{DD}$) scaling in conjunction with dimension scaling of transistors to reduce power consumption. However, reducing $V_{DD}$ and channel length ($L_{ch}$) typically…
The scaling of transistors to sub-10 nm dimensions is strongly limited by their contact resistance (Rc). Here we present a systematic study of scaling MoS2 devices and contacts with varying electrode metals and controlled deposition…
While cryogenic-temperature subthreshold swing (SS) in crystalline semiconductors has been widely studied, a careful study on the temperature-dependent SS in amorphous oxide semiconductors remains lacking. In this paper, a comprehensive…
Metal oxide (MO) semiconductors are widely used in electronic devices due to their high optical transmittance and promising electrical performance. This work describes the advancement toward an eco-friendly, streamlined method for preparing…
We present a scaling theory of two-dimensional (2D) field effect transistors (FETs). For devices with channel thickness less than 4 nm, the device electrostatics is dominated by the physical gate oxide thickness and not the effective oxide…
Carbon nanotube field-effect transistors with sub 20 nm long channels and on/off current ratios of > 1000000 are demonstrated. Individual single-walled carbon nanotubes with diameters ranging from 0.7 nm to 1.1 nm grown from structured…
While decreasing the oxide thickness in carbon nanotube field-effect transistors (CNFETs) improves the turn-on behavior, we demonstrate that this also requires scaling the range of the drain voltage. This scaling is needed to avoid an…
A new method to fabricate non-superconducting mesoscopic tunnel junctions by oxidation of Ti is presented. The fabrication process uses conventional electron beam lithography and shadow deposition through an organic resist mask.…
High performance InGaAs gate-all-around (GAA) nanowire MOSFETs with channel length (Lch) down to 20nm have been fabricated by integrating a higher-k LaAlO3-based gate stack with an equivalent oxide thickness of 1.2nm. It is found that…