Related papers: A radiation tolerant clock generator for the CMS E…

The Tile Calorimeter at ATLAS is a hadron calorimeter based on steel plates and scintillating tiles read out by PMTs. The current read-out system uses standard ADCs and custom ASICs to digitize and temporarily store the data on the…

The High Luminosity Large Hadron Collider (HL-LHC) at CERN is expected to collide protons at a center-of-mass energy of 14 TeV and to reach the unprecedented peak instantaneous luminosity of $7.5 \times 10^{34} \text{cm}^{-2} \text{s}^{-1}$…

Single electron Sensitive Read Out (SiSeRO) is a novel on-chip charge detector output stage for charge-coupled device (CCD) image sensors. Developed at MIT Lincoln Laboratory, this technology uses a p-MOSFET transistor with a depleted…

The cooling storage ring (CSR) external-target experiment (CEE) is a spectrometer running at the Heavy Ion Research Facility (HIRFL) at Lanzhou. The CEE is the first large-scale nuclear physics experimental device by China to operate in the…

The CSR External-target Experiment (CEE) will be the first large-scale nuclear physics experiment device at the Cooling Storage Ring (CSR) of the Heavy-Ion Research Facility in Lanzhou (HIRFL) in China. A new T0 detector has been proposed…

The first technological SDHCAL prototype having been successfully tested, a new phase of R&D, to validate completely the SDHCAL option for the International Linear Detector (ILD) project of the International Linear Collider (ILC), has…

ALICE, one of the experiments at the Large Hadron Collider (CERN), is undergoing ambitious upgrades during the ongoing second long shutdown (LS2). The main goal of this project is to access rare events and previously inaccessible physics…

A new silicon-strip readout chip named "SliT" has been developed for the measurement of the muon anomalous magnetic moment and electric dipole moment at J-PARC. The SliT is designed in the Silterra 180 nm CMOS technology with mixed-signal…

We propose without loss of generality strategies to achieve a high-throughput FPGA-based architecture for a QC-LDPC code based on a circulant-1 identity matrix construction. We present a novel representation of the parity-check matrix (PCM)…

In this article, we describe the key features of the recently completed technical design for the International Linear Collider (ILC), a 200-500 GeV linear electron-positron collider (expandable to 1 TeV) that is based on 1.3 GHz…

This paper presents the design and analysis of a wearable CMOS biosensor with three different designs of energy-resolution scalable time-based resistance to digital converters (RDC), targeted towards either minimizing the energy/conversion…

In recent years, SiPM photoelectric devices have drawn much attention in the domain of time-of-flight-based positron emission tomography (TOF-PET). Using them to construct PET detectors with excellent coincidence time resolution (CTR) is…

After the construction and successful operation of the first technological prototype of the Semi-Digital Hadronic CALorimeter (SDHCAL), developed within the CALICE collaboration, new R{\&}D efforts have been initiated to fully validate the…

This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver…

A monolithic silicon pixel prototype produced for the MONOLITH ERC Advanced project was irradiated with 70 MeV protons up to a fluence of 1 x 10^16 1 MeV n_eq/cm^2. The ASIC contains a matrix of hexagonal pixels with 100 {\mu}m pitch,…

The BICEP/Keck Collaboration is currently leading the quest to the highest sensitivity measurements of the polarized CMB anisotropies on degree scale with a series of cryogenic telescopes, of which BICEP Array is the latest Stage-3 upgrade…

An introduction and the status of R&D activities for a high-resolution, "cold" beam position monitor (BPM) and the related read-out electronics are discussed. Two different BPM detector concepts, to be attached to the SC quadrupole and…

Clock generation is an essential part of wireless or wireline communication modules. To facilitate recent advancements in wireline-like communication and in-sensor computing modules at relatively lower data rates, ultra-low power, and…

Multi-gap RPC prototypes with readout on a multi-strip electrode were developed for the small polar angle region of the CBM-TOF subdetector, the most demanding zone in terms of granularity and counting rate. The prototypes are based on low…

A 16-channel digital TDC chip has been built for the DIRC Cherenkov counter of the BaBar experiment at the SLAC B-factory (Stanford, USA). The binning is 0.5 ns, the conversion time 32 ns and the full-scale 32 mus. The data driven…