A new silicon-strip readout chip named "SliT" has been developed for the measurement of the muon anomalous magnetic moment and electric dipole moment at J-PARC. The SliT is designed in the Silterra 180 nm CMOS technology with mixed-signal integrated circuits. An analog circuit incorporates a conventional charge-sensitive amplifier, shaping amplifiers, and two distinct discriminators for each of 128 identical channels. A digital part includes storage memories, an event building block, a serializer, and LVDS drivers. A distinct feature of the SliT is utilization of the zero-cross architecture, which consists of a CR-RC filter followed by a CR circuit as a voltage differentiator. This architecture enables to generate hit signals with subnanosecond amplitude-independent time walk, which is the primary requirement for the experiment. The test results show the time walk of 0.38±0.16 ns between 0.5 and 3 MIP signals. The equivalent noise charge is 1547±75e− (rms) at Cdet=33 pF as a strip-sensor capacitance. Other functionalities such as a strip-sensor readout chip have also been proven in the tests. The SliT128C satisfies all requirements of the J-PARC muon g−2/EDM experiment.
@article{arxiv.2006.08095,
title = {SliT: A Strip-sensor Readout Chip with Subnanosecond Time-walk for the J-PARC Muon $g-2$/EDM Experiment},
author = {Tetsuichi Kishishita and Yutaro Sato and Yoichi Fujita and Eitaro Hamada and Tsutomu Mibe and Tsubasa Nagasawa and Shohei Shirabe and Masayoshi Shoji and Taikan Suehara and Manobu M. Tanaka and Junji Tojo and Yuki Tsutumi and Takashi Yamanaka and Tamaki Yoshioka},
journal= {arXiv preprint arXiv:2006.08095},
year = {2020}
}