Related papers: A radiation tolerant clock generator for the CMS E…

Development of readout electronics for Time Projection Chamber for a Linear Collider is ongoing under stringent requirements on high channel density, lowest possible power consumption and small material budget. In the studied TPC readout…

Resource constraints in smart devices demand an efficient cryptosystem that allows for low power and memory consumption. This has led to popularity of comparatively efficient Elliptic curve cryptog-raphy (ECC). Prior to this paper, much of…

Integrated circuits of photonic components are the goal of applied polaritonics. Here, we propose a compact clock generator based on an exciton-polariton micropillar, providing optical signal with modulation frequency up to 100 GHz. This…

The readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider requires a radiation-hard ADC. The design of a radiation-hard dual-channel 12-bit 40 MS/s pipeline ADC for this use is presented. The…

This manuscript reports a semiconductor-sensitized thermal cell (STC) that converts ambient heat into electrical power while simultaneously reducing its own temperature under isothermal conditions. Using a printable…

The electronics used in the data readout and triggering system for the Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider (LHC) particle accelerator at CERN are exposed to high radiation levels. This radiation can cause…

A large prototype of 1.3m3 was designed and built as a demonstrator of the semi-digital hadronic calorimeter (SDHCAL) concept proposed for the future ILC experiments. The prototype is a sampling hadronic calorimeter of 48 units. Each unit…

Transition-edge sensors (TESs) are sensitive devices for detecting photons from millimeter radiation to gamma rays. Their photon counting efficiency and collecting area benefit from large-array multiplexing scheme, and therefore the…

The CALICE technological RPC-based SDHCAL prototype that fullfils all the requirements of compactness, hermeticity and power budget of the future lepton accelerator experiments, has been extensively tested and has provided excellent results…

A front-end readout electronics system has been developed for silicon strip detectors. The system uses an application specific integrated circuit (ASIC) ATHED to realize multi-channel E&T measurement. The slow control of ASIC chips is…

An ASIC named CATIROC (Charge And Time Integrated Read Out Chip) has been developed for the next-generation neutrino experiments using a large number of photomultiplier tubes (PMTs). Each CATIROC provides the time and the charge…

A pico-second timing (PIST) front-end electronic chip has been developed using $55~\mathrm{nm}$ CMOS technology for future electron-positron collider experiments (namely Higgs factories). Extensive tests have been performed to evaluate the…

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will…

We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the…

In this paper, we present a dual-channel serializer ASIC, LOCx2, and its pin-compatible backup, LOCx2-130, for detector front-end readout. LOCx2 is fabricated in a 0.25-um Silicon-on-Sapphire CMOS process and each channel operates at 5.12…

A new design of highly granular hadronic calorimeter using Glass Resistive Plate Chambers (GRPCs) with embedded electronics has been proposed for the future International Linear Collider (ILC) experiments. It features a 2-bit threshold…

For precise start time determination a Beam Fragmentation T$_0$ Counter (BFTC) is under development for the Time-of-Flight Wall of the Compressed Baryonic Matter Spectrometer (CBM) at the Facility for Antiproton and Ion Research (FAIR) at…

The first generation of Single electron Sensitive Read Out (SiSeRO) amplifiers, employed as on-chip charge detectors for charge-coupled devices (CCDs) have demonstrated excellent noise and spectral performance: a responsivity of around 800…

The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on…

The aim of this study is to design and evaluate a simple free running Analog-Digital Converter (ADC) based on the Field Programmable Gate Array (FPGA) device to accomplish the energy and position readout of the silicon photomultiplier…