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Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V and 5V) are presented in this paper. Several PMOS and NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias…

This paper presents a physics-based model for the threshold voltage in bulk MOSFETs valid from room down to cryogenic temperature (4.2 K). The proposed model is derived from Poisson's equation including bandgap widening, intrinsic…

This work presents a self-heating study of a 40-nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel…

Cryogenic CMOS technology (cryo-CMOS) offers a scalable solution for quantum device interface fabrication. Several previous works have studied the characterization of CMOS technology at cryogenic temperatures for various process nodes.…

Conventional CMOS technology operated at cryogenic conditions has recently attracted interest for its uses in low-noise electronics. We present one of the first characterizations of 180 nm CMOS technology at a temperature of 100 mK,…

This paper presents the design and benchmarking of cryogenic bulk-FETs using an experimentally calibrated TCAD framework that integrates 2-D electrostatics and interface-trap effects from $T = 2$ K to 300 K. For a 28-nm node device, carrier…

This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300, 77 and 4.2…

This paper presents the characterization of microwave passive components, including metal-oxide-metal (MoM) capacitors, transformers, and resonators, at deep cryogenic temperature (4.2 K). The variations in capacitance, inductance and…

This paper presents an extensive characterization of the low-frequency noise (LFN) at room temperature (RT) and cryogenic temperature (4.2 K) of 40-nm bulk-CMOS transistors. The noise is measured over a wide range of bias conditions and…

Narrow-channel accumulated body nMOSFET devices with p-type side-gates surrounding the active area have been electrically characterized between 100 and 400 K with varied side-gate biasing (Vside). The subthreshold slope (SS) and drain…

Silicon carbide is a wide-bandgap semiconductor with an emerging CMOS technology platform and it is widely deployed in high power and harsh environment electronics. This material is also attracting interest for quantum technologies through…

The cryogenic performance of GaN-based HEMTs (high-electron-mobility transistors) is systematically investigated by the direct current (DC) and low-frequency noise (LFN) characteristics within the temperature (T) range from 300 K to 4.2 K.…

Previous cryogenic electronics studies are most above 4.2K. In this paper we present the cryogenic characterization of a 0.18{\mu}m standard bulk CMOS technology(1.8V and 5V) at sub-kelvin temperature around 270mK. PMOS and NMOS devices…

Wide attention has been focused on cryogenic CMOS (Cryo-CMOS) operation because of its wide application and the improvement of CMOS performance. However, hot carrier degradation (HCD) becomes worsening at cryogenic temperature, which…

When designing and studying circuits operating at cryogenic temperatures understanding local heating within the circuits is critical due to the temperature dependence of transistor and noise behavior. We have investigated local heating…

This brief reports the analytical modeling and measurements of the inflection in the MOSFET transfer characteristics at cryogenic temperatures. Inflection is the inward bending of the drain current versus gate voltage, which reduces the…

This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes.…

This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The…

In this paper, through careful calibration, we demonstrate the possibility of using a single set of models and parameters to model the ON current and Sub-threshold Slope (SS) of an nMOSFET at 300K and 5K using Technology Computer-Aided…

Accurate on-chip temperature sensing is critical for the optimal performance of modern CMOS integrated circuits (ICs), to understand and monitor localized heating around the chip during operation. The development of quantum computers has…