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Motivated by the stringent requirements of the Upstream Pixel (UP) tracker in the LHCb Upgrade II and the Inner Tracking detector (ITK) of the Circular Electron Positron Collider, the COFFEE series of pixel sensor chips have been developed…

A new TDC-chip is under development for the COMPASS experiment at CERN. The ASIC, which exploits the 0.6 micrometer CMOS sea-of-gate technology, will allow high resolution time measurements with digitization of 75 ps, and an unprecedented…

In this work, a 3.5 GS/s voltage-controlled oscillator (VCO) analog-to-digital converter (ADC) using multi-stage noise shaping (MASH) is presented. This 28nm CMOS ADC achieves second-order noise shaping in an easily-scalable, open-loop…

In this paper we present a novel high-resolution multi-channel FPGA-based time-to-digital converter (TDC). We designed and implemented a complex electronic circuit on the FPGA, whose overall accuracy is several orders of magnitude greater…

For 5G it will be important to leverage the available millimeter wave spectrum. To achieve an approximately omni- directional coverage with a similar effective antenna aperture compared to state of the art cellular systems, an antenna array…

With the new generation of the RPC, it is possible to work with induced signals of hundreds $\mu V$, hence the front-end electronics is an important and delicate part of the detector in order to get a detectable signal. The electronic chain…

The first generation of Single electron Sensitive Read Out (SiSeRO) amplifiers, employed as on-chip charge detectors for charge-coupled devices (CCDs) have demonstrated excellent noise and spectral performance: a responsivity of around 800…

A readout electronic with high time and energy resolution performance is designed for the SDD (Silicon Drift Detector) signals readout, which is aimed for X-ray pulsar based navigation (XNAV). For time measurement, the input signal is fed…

A Time to Digital Converter was designed (CMOS 0.35 $\mum) in order to be used in Liquid Xenon PET prototype. The circuit proved to be able to work at -120 degrees C, while showing a resolution of 250 ps. The circuit enables a low readout…

In this contribution, it is proposes to limit the quantization search space of a successive approximation analog-to-digital converter through an analytic derivation of maximum possible sample-to-sample variation. The presented example…

The basic principle of operation of silicon sensors with resistive read-out is built-in charge sharing. Resistive Silicon Detectors (RSD, also known as AC-LGAD), exploiting the signals seen on the electrodes surrounding the impact point,…

We present a high performance low-power digital base-band architecture, specially designed for an energy optimized duty-cycled wake-up receiver scheme. Based on a careful wake-up beacon design, a structured wake-up beacon detection…

The radiation hardness of passive CMOS pixel sensors fabricated in 150 nm LFoundry technology is investigated. CMOS process lines are especially of interest for large-scale silicon detectors as they offer high production throughput at…

Radiation measurement relies on pulse detection, which can be performed using various configurations of high-speed analog-to-digital converters (ADCs) and field-programmable gate arrays (FPGAs). For optimal power consumption, design…

Recent works propose neural network- (NN-) inspired analog-to-digital converters (NNADCs) and demonstrate their great potentials in many emerging applications. These NNADCs often rely on resistive random-access memory (RRAM) devices to…

Low-resolution analog-to-digital converters (ADCs) have emerged as an efficient solution for massive multiple-input multiple-output (MIMO) systems to reap high data rates with reasonable power consumption and hardware complexity. In this…

All-digital millimeter-wave (mmWave) massive multi-user multiple-input multiple-output (MU-MIMO) receivers enable extreme data rates but require high power consumption. In order to reduce power consumption, this paper presents the first…

A 6bit flash-ADC with 1.2GSps, wide analog bandwidth and low power, realized in a standard digital 0.13 $\mu$m CMOS copper technology is presented. Employing capacitive interpolation gives various advantages when designing for low power: no…

Many application domains face the challenges of high-power consumption and high computational demands, especially with the advancement in embedded machine learning and edge computing. Designing application-specific circuits is crucial to…

Employing low-resolution analog-to-digital converters (ADCs) for millimeter wave receivers with large antenna arrays provides opportunity to efficiently reduce power consumption of the receiver. Reducing ADC resolution, however, results in…