Many application domains face the challenges of high-power consumption and high computational demands, especially with the advancement in embedded machine learning and edge computing. Designing application-specific circuits is crucial to reducing hardware complexity and power consumption. In these perspectives, this paper presents the design of a Digital Time-to-Digital converter (DTDC) based on multiple delay line topologies. The DTDC is implemented in VHDL for the Xilinx Artix-7 AC701 FPGA device. Simulation results demonstrate the effectiveness of the circuit in converting the input period along a wide range up to 1ps. The designed circuit is implemented with less than 1% of the resource utilization on the target FPGA device.
@article{arxiv.2508.08725,
title = {Architecture and FPGA Implementation of Digital Time-to-Digital Converter for Sensing Applications},
author = {Zeinab Hijazi and Fatima Bzeih and Ali Ibrahim},
journal= {arXiv preprint arXiv:2508.08725},
year = {2025}
}