A high precision and high resolution time-to-digital converter (TDC) implemented in a 40 nm fabrication process Virtex-6 FPGA is presented in this paper. The multi-chain measurements averaging architecture is used to overcome the resolution limitation determined by intrinsic cell delay of the plain single tapped-delay chain. The resolution and precision are both improved with this architecture. In such a TDC, the input signal is connected to multiple tapped-delay chains simultaneously (the chain number is M), and there is a fixed delay cell between every two adjacent chains. Each tapped-delay chain is just a plain TDC and should generate a TDC time for a hit input signal, so totally M TDC time values should be got for a hit signal. After averaging, the final TDC time is obtained. A TDC with 3 ps resolution (i.e. bin size) and 6.5 ps precision (i.e. RMS) has been implemented using 8 parallel tapped-delay chains. Meanwhile the plain TDC with single tapped-delay chain yields 24 ps resolution and 18 ps precision.
@article{arxiv.1406.3789,
title = {A Multi-chain Measurements Averaging TDC Implemented in a 40 nm FPGA},
author = {Qi Shen and Shubin Liu and Binxiang Qi and Qi An and Shengkai Liao and Chengzhi Peng and Weiyue Liu},
journal= {arXiv preprint arXiv:1406.3789},
year = {2016}
}