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The Compressive Sensing (CS) framework aims to ease the burden on analog-to-digital converters (ADCs) by reducing the sampling rate required to acquire and stably recover sparse signals. Practical ADCs not only sample but also quantize each…

The proposed delta-sigma modulator ($\Delta\Sigma$M) based signal acquisition architecture uses a differential difference amplifier (DDA) customized for dual purpose roles, namely as instrumentation amplifier and as integrator of…

A new TDC chip has been developed for the COMPASS experiment at CERN. The resulting ASIC offers an unprecedented degree of flexibility and functionality. Its capability to handle highest hit and trigger input rates as well as its low power…

Monolithic Active Pixel Sensors (MAPS) in advanced CMOS imaging technologies are key to next-generation tracking systems for high-energy physics, where radiation hardness and precise vertex reconstruction are essential. As part of the ALICE…

Deep neural networks are widely deployed in many fields. Due to the in-situ computation (known as processing in memory) capacity of the Resistive Random Access Memory (ReRAM) crossbar, ReRAM-based accelerator shows potential in accelerating…

We present measurements with a GEM based TPC prototypes and the TimePix CMOS ASIC as charge collecting anode. Tests with a small prototype were performed in a 5 GeV electron beam at DESY. Different GEM orientations and geometries were…

Nowadays, millimeter-wave (mmWave) massive multiple-input multiple-output (MIMO) systems is a favorable candidate for the fifth generation (5G) cellular systems. However, a key challenge is the high power consumption imposed by its numerous…

The broad energy response, low electronic read noise, and good energy resolution have made X-ray Charge-Coupled Devices (CCDs) an obvious choice for developing soft X-ray astronomical instruments over the last half century. They also come…

Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are decisively more.…

The design and performance of wave union TDC implemented in a Lattice CertusPro-NX FPGA is discussed. This FPGA is available for radiation tolerant applications. The TDC is implemented with 16-channels and a 200 MHz reference clock. Each…

We present a comprehensive characterization of resistive PICOSEC Micromegas detector prototypes, tested under identical conditions, constant drift gap, field configurations, and photocathode at the CERN SPS H4 beam line. This work provides…

Building upon existing signal processing techniques and open-source software, this paper presents a baseline design for an RF System-on-Chip Frequency Division Multiplexed readout for a spatio-spectral focal plane instrument based on low…

Extremely low-resolution (e.g. one-bit) analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) can substantially reduce hardware cost and power consumption for MIMO radar especially with large scale antennas. In this…

The burgeoning interest within the space community in digital beamforming is largely attributable to the superior flexibility that satellites with active antenna systems offer for a wide range of applications, notably in communication…

Decentralized diagnostic testing that is accurate, portable, quantitative, and capable of making multiple simultaneous measurements of different biomarkers at the point-of-need remains an important unmet need in the post-pandemic world.…

As diminishing feature sizes drive down the energy for computations, the power budget for on-chip communication is steadily rising. Furthermore, the increasing number of cores is placing a huge performance burden on the network-on-chip…

We introduce the waveform capture device (WCD), a flexible measurement system capable of recording complex digital signals on trillionth-of-a-second (ps) time scales. The WCD is implemented via modular code on an off-the-shelf…

The rapid development of Artificial Intelligence (AI) and Internet of Things (IoT) increases the requirement for edge computing with low power and relatively high processing speed devices. The Computing-In-Memory(CIM) schemes based on…

1 ps timing resolution is the entry point to signature based searches relying on secondary/tertiary vertices and particle identification. We describe a preliminary design for PSEC5, an 8-channel 40 GS/s waveform-sampling ASIC in the TSMC 65…

A time-domain analog-weighted-sum calculation model based on a pulse-width modulation (PWM) approach is proposed. The proposed calculation model can be applied to any types of network structure including multi-layer feedforward networks. We…