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Nanoscale miniaturization has revolutionized the field of spintronics by enabling exponential growth in areal bit density. A similar leap is also expected in device speeds through successfully harnessing femtosecond magnetization dynamics.…

Traditional transistors based on complementary metal-oxide-semiconductor (CMOS) and metal-oxide-semiconductor field-effect transistors (MOSFETs) are facing significant limitations as device scaling reaches the limits of Moore's Law. These…

Complementary-metal-oxide-semiconductor (CMOS) is the most widely spread technology for integrated circuits fabrication. Each foundry offers different technology nodes that are characterized by the minimum feature size, which is the…

One of the ultimate goals of molecular electronics is to create technologies that will complement - and eventually supersede - Si-based microelectronics technologies. To reach this goal, electronic properties that mimic at least some of the…

The continuous scaling of semiconductor technology has pushed the footprint of logic devices below 50 nm. Currently, logic standard cells with one single fin are being investigated to increase the integration density, although such options…

Through self-consistent quantum transport simulations, we evaluate the RF performance of monolayer graphene FETs in the bias region of negative output differential resistance. We show that, compared to the region of quasi-saturation, a…

Ultrathin oxide semiconductors with sub-1-nm thickness are promising building blocks for ultrascaled field-effect transistor (FET) applications due to their resilience against short-channel effects, high air stability, and potential for…

In this work, we propose SEE-MCAM, scalable and compact multi-bit CAM (MCAM) designs that utilize the three-terminal ferroelectric FET (FeFET) as the proxy. By exploiting the multi-level-cell characteristics of FeFETs, our proposed SEE-MCAM…

In this paper, the time-dependent dielectric breakdown (TDDB) in sub-1-nm equivalent oxide thickness (EOT) n-type bulk FinFETs is studied. The gate stacks consist of an IMEC clean interfacial layer, atomic layer deposition HfO2 high-k and…

Tri-gate ferroelectric FETs with Hf0.5Zr0.5O2 gate insulator for memory and neuromorphic applications are fabricated and characterized for multi-level operation. The conductance and threshold voltage exhibit highly linear and symmetric…

Thompson-Lampard type calculable capacitors (TLCC) serve as electrical capacitance standards, enabling the realization of the farad in the International System of Units (SI) with a combined uncertainty on the order of one part in $10^8$.…

Here we present the first demonstration and in-depth study of unreleased acoustic resonators in 14nm FinFET technology in the IEEE X band, which offer a zero-barrier-to-entry solution for high Q, small footprint, resonant tanks integrated…

Enhancing power efficiency and performance in neuromorphic computing systems is critical for next-generation artificial intelligence applications. We propose the Nanoscale Side-contacted Field Effect Diode (S-FED), a novel solution that…

Electronic transport in semiconducting single-wall carbon nanotubes is studied by combined scanning gate microscopy and scanning impedance microscopy (SIM). Depending on the probe potential, SIM can be performed in both invasive and…

This paper proposes a novel foreground linearization scheme for a high-speed CS-DAC. The technique leverages neural networks (NNs) to derive a LUT that maps the inverse of the DAC transfer characteristic onto the input codes. The algorithm…

The effective potential of scalar quantum electrodynamics with N flavors of complex scalar fields is studied, by performing a self consistent 1/N expansion up to next to leading order in $1/N$. Starting from the broken phase at zero…

Binary Neural Networks (BNNs) have been shown to be robust to random bit-level noise, making aggressive voltage scaling attractive as a power-saving technique for both logic and SRAMs. In this work, we introduce the first fully programmable…

This letter analyzes the scaling property of nanowire (NW) phase change memory (PCM) using analytic and numerical methods. The scaling scenarios of the three widely-used NW PCM peration schemes (constant electric field, voltage, and…

We introduce a combined density functional theory (DFT) and non-equilibrium Green's function (NEGF) framework to compute the capacitance of nanocapacitors and directly extract the dielectric response of a sub-nanometer dielectric under…

Carbon Nanotube (CNT) is one of the most significant materials for the development of faster and improved performance of nano-scaled transistors. This paper aims at analyzing a trade-off between device performance and device size of CNT…