Related papers: The Investigation of Negative Capacitance Vertical…

Bandstructure effects in the electronic transport of strongly quantized silicon nanowire field-effect-transistors (FET) in various transport orientations are examined. A 10-band sp3d5s* semi-empirical atomistic tight-binding model coupled…

In this paper we propose a modified structure of TFET incorporating ferroelectric oxide as the complementary gate dielectric operating in negative capacitance zone, called the Negative Capacitance Tunnel FET (NCTFET). The proposed device…

Pulse-based studies of ferroelectric capacitor systems have been used by several groups to experimentally probe the mechanisms of apparent negative capacitance. In this paper, the behavior of such systems is modeled through SPICE simulation…

Using a tight-binding mode-space NEGF technique, we explore the essential physics, design and performance potential of the III-V core-shell (CS) nanowire (NW) heterojunction TFET. The CS TFET line-tunneling current increases significantly…

The cold source field-effect transistor (CSFET) is promising for reducing power dissipation in integrated circuits by engineering the density of states at the injecting source. Existing CSFET designs utilizing Dirac-source metals or…

This paper investigates the use of carbon nanotube field effect transistors (CNFETs) for the design of ternary full adder cells. The proposed circuits have been designed based on the unique properties of CNFETs such as having desired…

Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly-scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce…

A comprehensive study of the scaling of negative capacitance FinFET (NC-FinFET) is conducted with TCAD. We show that the NC-FinFET can be scaled to "2.1nm node" and almost "1.5nm node" that comes two nodes after the industry "3nm node,"…

Bandstructure effects in PMOS transport of strongly quantized silicon nanowire field-effect-transistors (FET) in various transport orientations are examined. A 20-band sp3d5s* spin-orbit-coupled (SO) atomistic tight-binding model coupled to…

On-chip learning in a crossbar array based analog hardware Neural Network (NN) has been shown to have major advantages in terms of speed and energy compared to training NN on a traditional computer. However analog hardware NN proposals and…

The miniaturization of transistors down to 5nm and beyond, plus the increasing complexity of integrated circuits, significantly aggravate short channel effects, and demand analysis and optimization of more design corners and modes.…

In application-specific designs, owing to the trade-off between power consumption and speed, optimization of various circuit parameters has become a challenging task. Several of the performance metrics, viz. energy efficiency, gain,…

As the technology node continues to shrink, nanosheet field effect transistors (NSFETs) and complementary FETs (CFETs) become valid candidates for the 3nm and sub-nanometre nodes. However, due to the shrinking device size, self-heating and…

Nominally undoped silicon nanowires (NW) were grown by catalytic chemical vapor deposition. The growth process was optimized to control the NWs diameters by using different Au catalyst thicknesses on amorphous SiO2, Si3N4, or crystalline-Si…

Carbon nanotube field-effect transistors (CNFET) emerge as a promising alternative to CMOS transistors for the much higher speed and energy efficiency, which makes the technology particularly suitable for building the energy-hungry last…

This paper presents a self-consistent numerical model for calculating the charge profile and gate capacitance and therefore obtaining C-V characterization for a gate-all-around graded nanowire MOSFET with a high mobility axially graded…

A physics-based compact model for silicon gate-all-around (GAA) nanowire tunneling FETs (NW-tFETs) with good accuracy has been developed by considering Phonon-Assisted Tunneling (PAT) and transition from Quantum Capacitance Limit (QCL) to…

The Hamiltonian size reduction method or the mode space method applicable to general heterogeneous structures is developed in this work. The effectiveness and accuracy of the method are demonstrated for four example devices of GaSb/InAs…

We report a method to pattern monolayer graphene nanoconstriction field effect transistors (NCFETs) with critical dimensions below 10 nm. NCFET fabrication is enabled by the use of feedback controlled electromigration (FCE) to form a…

We present a data-calibrated compact model of carbon nanotube (CNT) field-effect transistors (CNFETs) including contact resistance, direct source-to-drain and band-to-band tunneling currents. The model captures the effects of dimensional…