Related papers: 20 GHZ Low Noise LLRF System

The FLASH L-band (1.3 GHz) superconducting accelerator facility at DESY has a Low Level RF (LLRF) system that is similar to that envisioned for ILC. This system has extensive monitoring capability and was used to gather performance data…

We present an overview of the 'ICE' hardware and software framework that implements large arrays of interconnected FPGA-based data acquisition, signal processing and networking nodes economically. The system was conceived for application to…

This article presents an approach to control the operating frequency and fractional bandwidth (FBW) of miniature acoustic filters in thin-film lithium niobate (TFLN). More specifically, we used first-order antisymmetric (A1) mode…

A novel design for a low dropout (LDO) voltage regulator is presented and dedicated to power many sections of a typical cellular handset. However, these baseband, RF, and audio sections have different requirements that influence which LDO…

We designed and implemented a deep learning based RF signal classifier on the Field Programmable Gate Array (FPGA) of an embedded software-defined radio platform, DeepRadio, that classifies the signals received through the RF front end to…

A 16-element, compact phased array transceiver is demonstrated at E-band (71-76 and 81-86GHz). A Weaver image selection architecture reduces the LO tuning range to 3GHz while covering the 10GHz band. The bidirectional and efficient…

With the evolution of heterogeneous computing system, such as network-on-chip, high-performance distributed computing, accelerator-rich architectures and cluster computing, high-speed, energy-efficient and low-latency interfaces among…

A field programmable gate array (FPGA) based timing and trigger control system has been developed for the Dynamic Compression Sector (DCS) user facility located at the Advanced Photon Source (APS) at Argonne National Laboratory. The DCS is…

One of the major challenges in communication, radar, and electronic warfare receivers arises from nearby device interference. The paper presents a 2-6 GHz GaN LNA front-end with onboard sensing, processing, and feedback utilizing…

Control electronics for superconducting quantum processors have strict requirements for accurate command of the sensitive quantum states of their qubits. Hinging on the purity of ultra-phase-stable oscillators to upconvert very-low-noise…

In this paper, we combine the design of band-pass frequency selective surfaces (FSSs) with polarization converters to realize a broadband frequency-selective polarization converter (FSPC) with lowbackward scattering, which consists of the…

This contribution focuses on phase-noise added during frequency conversion in low-level radio frequency (LLRF) control systems. The stability of beams' parameters in linear accelerators depends on the stability of amplitude and phase of the…

We propose without loss of generality strategies to achieve a high-throughput FPGA-based architecture for a QC-LDPC code based on a circulant-1 identity matrix construction. We present a novel representation of the parity-check matrix (PCM)…

Time-to-digital converters (TDCs) are used in various fields, including high-energy physics. One advantage of implementing TDCs in field-programmable gate arrays (FPGAs) is the flexibility on the modification of the logics, which is useful…

A Low-Power Variable Gain (VG) mm-Wave Low Noise Amplifier (LNA) is designed and simulated in a 28-nm CMOS process. The LNA utilizes a simple, yet novel, technique presented in this paper to vary the small-signal output resistance to…

A near memory hardware accelerator, based on a novel direct path computational model, for real-time emulation of radio frequency systems is demonstrated. Our evaluation of hardware performance uses both application-specific integrated…

Conventional analog-to-digital converters (ADCs) fail to capture high-dynamic-range (HDR) signals due to clipping. Modulo ADCs circumvent this limitation by folding the input prior to quantization and algorithmically reconstructing the…

In recent years the computational capacity of single Field Programmable Gate Arrays (FPGA) devices as well as their versatility has increased significantly. Adding to that the High Level Synthesis frameworks allowing to program such…

The operation of CMOS Field Programmable Gate Arrays (FPGAs) at extremely cold environments as low as 4 K is demonstrated. Various FPGA and periphery hardware design techniques spanning from HDL design to improvements of peripheral…

In this paper, we propose a dual-hop RF (Radio-Frequency)/FSO (Free-Space Optical) system with multiple relays employing the Decode-and-Forward (DF) and Amplify-and-Forward (AF) with a Fixed Gain (FG) relaying scheme. The RF channels are…