Related papers: Implementation of the Logistic Map with FPGA using…
In this paper, one can explicitly see the process of implementing the robust residual generator on digital domain, especially on FPGA. Firstly, the baseline model is developed in double precision floating point format. To develop the…
The increasing demand of dedicated accelerators to improve energy efficiency and performance has highlighted FPGAs as a promising option to deliver both. However, programming FPGAs in hardware description languages requires long time and…
This paper reviews memory technologies used in Field-Programmable Gate Arrays (FPGAs) for neuromorphic computing, a brain-inspired approach transforming artificial intelligence with improved efficiency and performance. It focuses on the…
The implementation of fault-tolerant quantum gates on encoded logic qubits is considered. It is shown that transversal implementation of logic gates based on simple geometric control ideas is problematic for realistic physical systems…
Physical Unclonable Functions (PUFs) leverage signal variations that occur within the device as a source of entropy. On-chip instrumentation is utilized by some PUF architectures to measure and digitize these variations, which are then…
In this paper, we propose an architecture/methodology for making FPGAs suitable for integer as well as variable precision floating point multiplication. The proposed work will of great importance in applications which requires variable…
Security issues are playing dominant role in today's high speed communication systems. A fast and compact FPGA based implementation of the Data Encryption Standard (DES) and Triple DES algorithm is presented in this paper that is widely…
It is highly predicted that the roads and parking areas will be extremely congested with vehicles to the point that searching for a novel solution will not be an optional choice for conserving the sustainability rate of the overall…
The advent of computationally demanding algorithms and high data rate instruments in new space applications pushes the space industry to explore disruptive solutions for on-board data processing. We examine heterogeneous computing…
Modern Graphics Processing Units (GPUs) are now considered accelerators for general purpose computation. A tight interaction between the GPU and the interconnection network is the strategy to express the full potential on capability…
We propose without loss of generality strategies to achieve a high-throughput FPGA-based architecture for a QC-LDPC code based on a circulant-1 identity matrix construction. We present a novel representation of the parity-check matrix (PCM)…
The use and location of memory in integrated circuits plays a key factor in their performance. Memory requires large physical area, access times limit overall system performance and connectivity can result in large fan-out. Modern FPGA…
Like other automated system technologies, PROFINET, a real-time Industrial Ethernet Standard has shown increasing level of integration into the present IT Infrastructure. Such vast use of PROFINET can expose the controllers and I/O devices…
This study introduces a lightweight U-Net model optimized for real-time semantic segmentation of aerial images, targeting the efficient utilization of Commercial Off-The-Shelf (COTS) embedded computing platforms. We maintain the accuracy of…
Modern SoC-FPGA that consists of FPGA with embedded ARM cores is being popularized as an embedded vision system platform. However, the design approach of SoC-FPGA applications still follows traditional hardware-software separate workflow,…
In this paper, we propose an architecture for FPGA emulation of mixed-signal systems that achieves high accuracy at a high throughput. We represent the analog output of a block as a superposition of step responses to changes in its analog…
This paper presents a method to stabilize state and input constrained nonlinear systems using an offline optimization on variable triangulations of the set of admissible states. For control-affine systems, by choosing a continuous piecewise…
As the increasing complexity of Neural Network(NN) models leads to high demands for computation, AMD introduces a heterogeneous programmable system-on-chip (SoC), i.e., Versal ACAP architectures featured with programmable logic (PL), CPUs,…
Hardware acceleration has emerged as a key research topic for supporting computationally intensive signal processing and artificial intelligence applications in 6G research and development studies. This paper presents an RF Network on Chip…
The coordinate rotation digital computer (CORDIC) is a shift-add based fast computing algorithm which has been found in many digital signal processing (DSP) applications. In this paper, a detailed error analysis based on mean square error…