In this paper, we propose an architecture/methodology for making FPGAs suitable for integer as well as variable precision floating point multiplication. The proposed work will of great importance in applications which requires variable precision floating point multiplication such as multi-media processing applications. In the proposed architecture/methodology, we propose the replacement of existing 18x18 bit and 25x18 bit dedicated multipliers in FPGAs with dedicated 24x24 bit and 24x9 bit multipliers, respectively. We have proved that our approach of providing the dedicated 24x24 bit and 24x9 bit multipliers in FPGAs will make them efficient for performing integer as well as single precision, double precision, and Quadruple precision floating point multiplications.
@article{arxiv.0711.2671,
title = {Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs},
author = {Himanshu Thapliyal and Hamid R. Arabnia and Rajnish Bajpai and Kamal K. Sharma},
journal= {arXiv preprint arXiv:0711.2671},
year = {2007}
}
Comments
Published in Proceedings of the 2007 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'07), Las Vegas, U.S.A, June 2007, Volume 1, pp. 449-450.(CSREA Press)