Related papers: EffiTest: Efficient Delay Test and Statistical Pre…

At submicron manufacturing technology nodes process variations affect circuit performance significantly. This trend leads to a large timing margin and thus overdesign to maintain yield. To combat this pessimism, post-silicon clock tuning…

At submicron manufacturing technology nodes, pro- cess variations affect circuit performance significantly. To counter these variations, engineers are reserving more timing margin to maintain yield, leading to an unaffordable overdesign.…

Post-Silicon Tunable (PST) clock buffers are widely used in high performance designs to counter process variations. By allowing delay compensation between consecutive register stages, PST buffers can effectively improve the yield of digital…

Post-silicon clock tuning elements are widely used in high-performance designs to mitigate the effects of process variations and aging. Located on clock paths to flip-flops, these tuning elements can be configured through the scan chain so…

In post-silicon validation, tuning is to find the values for the tuning knobs, potentially as a function of process parameters and/or known operating conditions. In this sense, an more efficient tuning requires identifying the most critical…

The scan-based testing has been widely used as a Design-for-Test (DfT) mechanism for most recent designs. It has gained importance not only in manufacturing testing but also in online testing and debugging. However, the multiplexer-based…

Transient stability assessment is a critical tool for power system design and operation. With the emerging advanced synchrophasor measurement techniques, machine learning methods are playing an increasingly important role in power system…

This paper proposes an algorithm for synthesis of clock-follow-data designs that provides robustness against timing violations for RSFQ circuits while maintaining high performance and minimizing area costs. Since superconducting logic gates…

The semiconductor chip manufacturing process is complex and lengthy, and potential errors arise at every stage. Each wafer contains numerous chips, and wafer bin maps can be generated after chip testing. By analyzing the defect patterns on…

Post-silicon validation is one of the most critical processes in modern semiconductor manufacturing. Specifically, correct and deep understanding in test cases of manufactured devices is key to enable post-silicon tuning and debugging. This…

In this paper a new optimum tuning method of PI controllers in first-order time-delay systems, based on the deadbeat response to a step setpoint variation, is presented. The deadbeat performance, already studied for the plants without…

Since the advent of new nanotechnologies, the variability of gate delay due to process variations has become a major concern. This paper proposes a new gate delay model that includes impact from both process variations and multiple input…

The development of exascale and post-exascale HPC and AI systems integrates thousands of CPUs and specialized accelerators, making energy optimization critical as power costs rival hardware expenses. To reduce consumption, frequency and…

This paper presents new fast exact feasibility tests for uniprocessor real-time systems using preemptive EDF scheduling. Task sets which are accepted by previously described sufficient tests will be evaluated in nearly the same time as with…

In Real-time system, utilization based schedulability test is a common approach to determine whether or not tasks can be admitted without violating deadline requirements. The exact problem has previously been proven intractable even upon…

With the outsourcing of design flow, ensuring the security and trustworthiness of integrated circuits has become more challenging. Among the security threats, IC counterfeiting and recycled ICs have received a lot of attention due to their…

We have investigated instability of a superconducting quantum computer by continuously monitoring the qubit output. We found that qubits exhibit a step-like change in the error rates. This change is repeatedly observed, and each step…

We present systematic and efficient solutions for both observability enhancement and root-cause diagnosis of post-silicon System-on-Chips (SoCs) validation with diverse usage scenarios. We model specification of interacting flows in typical…

Adiabatic Quantum-Flux-Parametron (AQFP) logic is a promising emerging device technology with six orders of magnitude lower power than CMOS. However, AQFP is challenged by the fact that every gate must be clocked, where proper data transfer…

By advances in technology, integrated circuits have come to include more functionality and more complexity in a single chip. Although methods of testing have improved, but the increase in complexity of circuits, keeps testing a challenging…