In post-silicon validation, tuning is to find the values for the tuning knobs, potentially as a function of process parameters and/or known operating conditions. In this sense, an more efficient tuning requires identifying the most critical tuning knobs and process parameters in terms of a given figure-of-merit for a Device Under Test (DUT). This is often manually conducted by experienced experts. However, with increasingly complex chips, manual inspection on a large amount of raw variables has become more challenging. In this work, we leverage neural networks to efficiently select the most relevant variables and present a corresponding deep-learning-aided pipeline for efficient tuning.
@article{arxiv.2207.00336,
title = {A Deep-Learning-Aided Pipeline for Efficient Post-Silicon Tuning},
author = {Yiwen Liao and Bin Yang and Raphaël Latty and Jochen Rivoir},
journal= {arXiv preprint arXiv:2207.00336},
year = {2022}
}
Comments
Accepted by the 34th workshop on Test Methods and Reliability of Circuits and Systems 2022